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| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2025-02-04 14:40:07 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-02-06 12:01:34 +0100 |
| commit | d0f17738778c12be629ba77ff00c43c3e9eb8428 (patch) | |
| tree | 73737edef7917f78520a0c95b0a21db99a5e5906 /tools/perf/scripts/python | |
| parent | arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi (diff) | |
| download | linux-d0f17738778c12be629ba77ff00c43c3e9eb8428.tar.gz linux-d0f17738778c12be629ba77ff00c43c3e9eb8428.zip | |
arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI0 PHY.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions