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| author | José Roberto de Souza <jose.souza@intel.com> | 2018-12-03 16:33:59 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2018-12-04 12:12:32 -0800 |
| commit | d15f9cdd59bab73e7edadee794efdd47bcbc1a7a (patch) | |
| tree | 05b964777391579c996e46defffab200477eb56d /tools/perf/scripts/python | |
| parent | drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch (diff) | |
| download | linux-d15f9cdd59bab73e7edadee794efdd47bcbc1a7a.tar.gz linux-d15f9cdd59bab73e7edadee794efdd47bcbc1a7a.zip | |
drm/i915/icl: Do not change reserved registers related to PSR2
For ICL the bit 12 of CHICKEN_TRANS is reserved so we should not
touch it and as by default VSC_DATA_SEL_SOFTWARE_CONTROL is already
unset in gen10 + GLK we can just drop it and fix for both gens.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181204003403.23361-5-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions