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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2014-07-04 11:50:31 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-23 07:05:32 +0200 |
| commit | d49bdb0e1054d022cc6f88fcecf9c79bae66eab0 (patch) | |
| tree | db3e2bc2ce5e819705c1ebf21e10bec934dce8ad /tools/perf/scripts/python | |
| parent | drm/i915: HSW_BLC_PWM2_CTL doesn't exist on BDW (diff) | |
| download | linux-d49bdb0e1054d022cc6f88fcecf9c79bae66eab0.tar.gz linux-d49bdb0e1054d022cc6f88fcecf9c79bae66eab0.zip | |
drm/i915: extract and improve gen8_irq_power_well_post_enable
Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
so we can reuse the nice IRQ macros we have there. The main difference
is that now we're going to check if the IIR register is non-zero when
we try to re-enable the interrupts.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions