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| author | Leo Chen <sancchen@amd.com> | 2023-07-12 16:50:15 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-07-25 16:21:54 -0400 |
| commit | de612738e9771bd66aeb20044486c457c512f684 (patch) | |
| tree | ec844ed0524029f81a3bf5d22fb4f2cfd4300c20 /tools/perf/scripts/python | |
| parent | drm/amd/display: Don't apply FIFO resync W/A if rdivider = 0 (diff) | |
| download | linux-de612738e9771bd66aeb20044486c457c512f684.tar.gz linux-de612738e9771bd66aeb20044486c457c512f684.zip | |
drm/amd/display: Exit idle optimizations before attempt to access PHY
[Why & How]
DMUB may hang when powering down pixel clocks due to no dprefclk.
It is fixed by exiting idle optimization before the attempt to access PHY.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions