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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2014-05-28 22:40:13 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-22 13:17:12 -0500 |
| commit | e9f9fe35f8940c9a4c5deba091d532e3a02bf78b (patch) | |
| tree | 92039dc9e2c43c36299e16c3f0412f6ab5a62b96 /tools/perf/scripts/python | |
| parent | ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk (diff) | |
| download | linux-e9f9fe35f8940c9a4c5deba091d532e3a02bf78b.tar.gz linux-e9f9fe35f8940c9a4c5deba091d532e3a02bf78b.zip | |
ARM: socfpga: dts: Fix gpio dts entry for the correct clock
The correct clock for the HPS gpio(s) should be the l4_mp_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions