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| author | Will Deacon <will.deacon@arm.com> | 2011-07-19 22:43:28 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2011-08-31 10:18:01 +0100 |
| commit | ecf5a893211c26e02b9d4cfd6ba2183473ac0203 (patch) | |
| tree | accf48ac99027c2b3fcc81217569abae827ad80d /tools/perf/scripts/python | |
| parent | ARM: perf: index Xscale and ARMv6 event counters starting from zero (diff) | |
| download | linux-ecf5a893211c26e02b9d4cfd6ba2183473ac0203.tar.gz linux-ecf5a893211c26e02b9d4cfd6ba2183473ac0203.zip | |
ARM: perf: index PMU registers from zero
ARM PMU code used to use 1-based indices for PMU registers. This caused
several data structures (pmu_hw_events::{active_events, used_mask, events})
to have an unused element at index zero. ARMPMU_MAX_HWEVENTS still takes
this indexing into account, and currently equates to 33.
This patch updates the core ARM perf code to use the 0th index again.
Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions