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| author | Cezary Rojewski <cezary.rojewski@intel.com> | 2019-07-23 16:58:50 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-07-24 19:42:09 +0100 |
| commit | f2a167ca681d21aa46f127032cc005879c328823 (patch) | |
| tree | dc0e87bd791f97dc1049a6eb9ee77a4fd561c983 /tools/perf/scripts/python | |
| parent | 88abcc90cb04cbabcc3e384e8d3431a49f56a2b3 (diff) | |
| download | linux-f2a167ca681d21aa46f127032cc005879c328823.tar.gz linux-f2a167ca681d21aa46f127032cc005879c328823.zip | |
ASoC: Intel: Skylake: Remove MCPS available check
The entire logic for MCPS calculation and DSP scheduling is found
within DSP firmware. Currently driver implements simplistic, inaccurate
logic itself which may prevent pipeline creation despite firmware being
completely fine its parameters.
Remove that logic and leave the MCPS calculation to DSP alone.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20190723145854.8527-4-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions