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authorVille Syrjälä <ville.syrjala@linux.intel.com>2021-10-07 02:57:01 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2021-10-18 12:23:40 +0300
commitf9a7b19c484067fdcc5972c88ab6f06898adc40d (patch)
tree2075f307e71bd703df8ebbaf0037b74906dec0d8 /tools/perf/scripts/python
parentdrm/i915: Avoid bitwise vs logical OR warning in snb_wm_latency_quirk() (diff)
downloadlinux-f9a7b19c484067fdcc5972c88ab6f06898adc40d.tar.gz
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drm/i915: Move the pxp plane state computation
No real reason to have this pxp state computation in intel_atomic_check_planes(). Just stuff it into skl_plane_check(). There was also some funny state copying being done from the old plane state to the new plane state when the plane is anyway disabled. The one thing we presumably must remember to do is copy over the decrypt state when assigning a Y plane for planar YCbCr scanout, so that the Y plane's PLANE_SURF will get the appropriate bit set. The force_black thing should not matter as I'm pretty sure all that stuff is ignored for the Y plane. I suppose this was the reason for the odd placement for the state computation, but I see no reason to deviate from the standard way of doing these things. This also guarantees that we don't calculate things differently between the linked UV and Y plane. v2: Only do stuff for icl+ since 'force_black' depends on the plane CSC which is an icl+ feature Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Juston Li <juston.li@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211006235704.28894-2-ville.syrjala@linux.intel.com Reviewed-by: Juston Li <juston.li@intel.com> #v1
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