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| author | Mike Marciniszyn <mike.marciniszyn@intel.com> | 2018-06-20 09:43:06 -0700 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@mellanox.com> | 2018-06-22 09:12:17 -0600 |
| commit | 06e81e3e920806593fa7459ee52bf9b978a8d260 (patch) | |
| tree | 610aacb4de047e2767cb3e6908fe7205a5a7e693 /tools/perf/scripts | |
| parent | 15d063d5db188b3d6ef5c5d73d59b47895454861 (diff) | |
| download | linux-06e81e3e920806593fa7459ee52bf9b978a8d260.tar.gz linux-06e81e3e920806593fa7459ee52bf9b978a8d260.zip | |
IB/hfi1: Remove caches of chip CSRs
Remove the sizeable cache of the chip sizing CSRs and replace with CSR
reads as needed.
Reviewed-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Diffstat (limited to 'tools/perf/scripts')
0 files changed, 0 insertions, 0 deletions