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| author | Rohit Khaire <rohit.khaire@amd.com> | 2021-06-04 11:32:42 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-04 16:02:50 -0400 |
| commit | cec7e80fbff58cdfd6595e7d11d7b2a38545c2e4 (patch) | |
| tree | 99c984824bad17e40c44c621048b86b5eeae3fb2 /tools/perf/scripts | |
| parent | drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid (diff) | |
| download | linux-cec7e80fbff58cdfd6595e7d11d7b2a38545c2e4.tar.gz linux-cec7e80fbff58cdfd6595e7d11d7b2a38545c2e4.zip | |
drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid
Enable this only for Sienna Cichild
since only Navi12 and Sienna Cichlid support SRIOV
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts')
0 files changed, 0 insertions, 0 deletions