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generated by cgit v1.2.3 (git 2.39.1) at 2026-01-14 14:26:40 +0000
mit/drivers/clk/meson/meson8b-clkc.c?id=a718ce38d4cdcd1377d5b2e40b10acd80e63af29&follow=1'>clk: meson8b: make it explicitly non-modularPaul Gortmaker1-15/+4 2016-07-01clk: qcom: add EBI2 clocks to the MSM8660 GCCLinus Walleij1-0/+28 2016-07-01clk: imx7d: only enable minimum required clocksDong Aisheng1-8/+10 2016-07-01clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLEDong Aisheng1-357/+357 2016-07-01clk: imx: add clk api for supporting CLK_OPS_PARENT_ENABLE clocksDong Aisheng1-0/+32 2016-07-01clk: imx: re-order and concentrate the same type of clk apiDong Aisheng1-29/+29 2016-07-01clk: core: support clocks which requires parents enable (part 2)Dong Aisheng1-15/+33 2016-07-01clk: core: support clocks which requires parents enable (part 1)Dong Aisheng2-0/+7 2016-07-01clk: move clk_disable_unused after clk_core_disable_unprepare functionDong Aisheng1-98/+98 2016-07-01clk: introduce clk_core_enable_lock and clk_core_disable_lock functionsDong Aisheng1-22/+63 2016-07-01clk: fixed-factor: Allow for a few clocks to change the parent rateMaxime Ripard2-1/+14 2016-07-01clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bitsXing Zheng1-1/+1 2016-07-01clk: rockchip: export rk3228 MAC clocksXing Zheng1-11/+11 2016-07-01clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclkXing Zheng1-3/+3 2016-07-01clk: rockchip: export rk3228 audio clocksXing Zheng1-4/+4 2016-07-01clk: rockchip: include rk3228 downstream muxes into fractional dividersXing Zheng1-29/+52 2016-06-30clk: fixed-rate: add clk_hw_unregister_fixed_rate()Masahiro Yamada2-0/+12 2016-06-30clk: hisilicon: hi3519: add driver remove path and fix some issuesJiancheng Xue1-16/+100 2016-06-30clk: hisilicon: add hisi_clk_unregister_* functionsJiancheng Xue1-0/+21 2016-06-30clk: hisilicon: add error processing for hisi_clk_register_* functionsJiancheng Xue2-15/+55 2016-06-30clk: hisilicon: add hisi_clk_alloc function.Jiancheng Xue2-0/+32 2016-06-30reset: hisilicon: change the definition of hisi_reset_initJiancheng Xue3-13/+13 2016-06-30clk: s2mps11: Migrate to clk_hw based OF and registration APIsStephen Boyd1-12/+9 2016-06-30clk: stm32f4: Migrate to clk_hw based OF and registration APIsStephen Boyd1-6/+6 2016-06-30clk: bcm: iproc: Migrate to clk_hw based registration and OF APIsStephen Boyd3-35/+33 2016-06-30clk: u300: Migrate to clk_hw based registration APIsStephen Boyd1-26/+33 2016-06-30clk: nomadik: Migrate to clk_hw based OF and registration APIsStephen Boyd1-22/+26 2016-06-30clk: highbank: Migrate to clk_hw based registration and OF APIsStephen Boyd1-5/+4 2016-06-30clk: st: clkgen-pll: Detect critical clocksLee Jones1-10/+17 2016-06-30clk: st: clkgen-fsyn: Detect critical clocksLee Jones1-3/+7 2016-06-30clk: st: clk-flexgen: Detect critical clocksLee Jones1-1/+3 2016-06-30clk: hi6220: Add RTC clock for pl031Zhangfei Gao2-2/+5 2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker6-598/+531 2016-06-28clk: Provide notifier stubs when !COMMON_CLKKrzysztof Kozlowski1-2/+14 2016-06-28clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996Stephen Boyd1-16/+0 2016-06-23clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding1-4/+4 2016-06-23clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding1-2/+2 2016-06-22clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette5-0/+1245