aboutsummaryrefslogtreecommitdiffstats
path: root/tools/perf/scripts/python/netdev-times.py
diff options
context:
space:
mode:
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.3 (git 2.39.1) at 2026-02-03 09:21:16 +0000
n> 2017-06-21clk: uniphier: provide NAND controller clock rateMasahiro Yamada1-4/+11 2017-06-21clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue2-1/+29 2017-06-21clk: Add Gemini SoC clock controllerLinus Walleij3-0/+464 2017-06-21clk: iproc: Remove __init marking on iproc_pll_clk_setup()Stephen Boyd1-6/+6 2017-06-19clk: bcm: Add clocks for Stingray SOCSandeep Tripathy3-0/+336 2017-06-19dt-bindings: clk: Extend binding doc for Stingray SOCSandeep Tripathy2-0/+177 2017-06-19clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang2-1/+26 2017-06-19clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang2-1/+10 2017-06-19clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang3-1/+151 2017-06-19clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven1-1/+1 2017-06-19clk: hi6220: add acpu clockZhangfei Gao3-0/+27 2017-06-19clk: zx296718: export I2S mux clocksShawn Guo2-5/+9 2017-06-19clk: imx7d: create clocks behind rawnand clock gateStefan Agner2-3/+7 2017-06-19clk: hi3660: Set PPLL2 to 2880MZhong Kaihua1-2/+2 2017-06-19clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun2-0/+57 2017-06-19clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun1-2/+4 2017-06-19clk: gcc-msm8916: add support to 9.6MHz codec clkSrinivas Kandagatla1-0/+1 2017-06-19clk: qcom: Add ipq8074 Global Clock Controller supportAbhishek Sahu3-0/+1017 2017-06-19clk: qcom: Add DT bindings for ipq8074 gcc clock controllerAbhishek Sahu2-0/+153