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='nohover-highlight'> Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> 2009-06-19OMAP3 SRAM: convert SRAM code to use macros rather than magic numbersPaul Walmsley1-15/+38 Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: Paul Walmsley <paul@pwsan.com> 2009-06-19OMAP3 SRAM: add more comments on the SRAM codePaul Walmsley1-21/+24 Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: Paul Walmsley <paul@pwsan.com> 2009-06-19OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock changePaul Walmsley4-8/+14 Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com> 2009-06-19OMAP3 clock: add a short delay when lowering CORE clk ratePaul Walmsley4-18/+44 When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com> 2009-06-19OMAP3 clock: initialize SDRC timings at kernel startPaul Walmsley2-3/+36 On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley <paul@pwsan.com> 2009-06-19OMAP3 clock: remove wait for DPLL3 M2 clock to stabilizePaul Walmsley1-3/+0 The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: Paul Walmsley <paul@pwsan.com>