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git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"A couple of new device support and small driver updates for this
round.
New support:
- Intel idxd Wildcat Lake family support
- SpacemiT K1 PDMA controller support
- Renesas RZ/G3E family support
Updates:
- Xilinx shutdown support and dma client properties update
- Designware edma callback_result support"
* tag 'dmaengine-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
dt-bindings: dma: rz-dmac: Document RZ/G3E family of SoCs
dmaengine: dw-edma: Set status for callback_result
dmaengine: mv_xor: match alloc_wc and free_wc
dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing
dmaengine: mmp_pdma: Add operations structure for controller abstraction
dmaengine: mmp_pdma: Add reset controller support
dmaengine: mmp_pdma: Add clock support
dt-bindings: dma: Add SpacemiT K1 PDMA controller
dt-bindings: dmaengine: xilinx_dma: Remove DMA client properties
dmaengine: Fix dma_async_tx_descriptor->tx_submit documentation
dmaengine: xilinx_dma: Support descriptor setup from dma_vecs
dmaengine: sh: setup_xref error handling
dmaengine: Replace zero-length array with flexible-array
dmaengine: ppc4xx: Remove space before newline
dmaengine: idxd: Add a new IAA device ID for Wildcat Lake family platforms
dmaengine: idxd: Replace memset(0) + strscpy() with strscpy_pad()
dt-bindings: dma: nvidia,tegra20-apbdma: Add undocumented compatibles and "clock-names"
dmaengine: zynqmp_dma: Add shutdown operation support
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.
Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.
Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.
Driver updates in the cache controller, memory controller and reset
controller subsystems.
SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.
TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"
* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...
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After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,admac" anymore [1]. Use
"apple,t8103-admac" as base compatible as it is the SoC the driver and
bindings were written for.
admac on Apple's M2 Pro/Max/Ultra SoCs is compatible with
"apple,t8103-admac" so add its per-SoC compatible with the former as
fallback used by the existing driver.
[1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/
Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Janne Grunau <j@jannau.net>
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The DMAC block on the RZ/G3E SoC is identical to the one found on the
RZ/V2H(P) SoC.
No driver changes are required, as `renesas,r9a09g057-dmac` will be used
as a fallback compatible string on the RZ/G3E SoC.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250801084825.471011-3-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add device tree binding documentation for the SpacemiT K1 PDMA
controller.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250822-working_dma_0701_v2-v5-1-f5c0eda734cc@riscstar.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Remove DMA client section mentioned in the dt-bindings as it is
not required to document client bindings in dmaengine bindings.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Link: https://lore.kernel.org/r/20250825130423.5739-1-abin.joseph@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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"clock-names"
Add the undocumented NVIDIA APBDMA compatibles and "clock-names" which
are already in use. There doesn't appear to be any per compatible
differences.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250812203308.727731-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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num-channels and qcom,num-ees are required when there are no clocks
specified in the device tree, because we have no reliable way to read them
from the hardware registers if we cannot ensure the BAM hardware is up when
the device is being probed.
This has often been forgotten when adding new SoC device trees, so make
this clear by describing this requirement in the schema.
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250212-bam-dma-fixes-v1-7-f560889e65d8@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"Core:
- Managed API for dma channel request
New support:
- Sophgo CV18XX/SG200X dmamux driver
- Qualcomm Milos GPI, sc8280xp GPI support
Updates:
- Conversion of brcm,iproc-sba and marvell,orion-xor binding
- Unused code cleanup across drivers"
* tag 'dmaengine-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (23 commits)
dt-bindings: dma: fsl-mxs-dma: allow interrupt-names for fsl,imx23-dma-apbx
dmaengine: xdmac: make it selectable for ARCH_MICROCHIP
dt-bindings: dma: Convert marvell,orion-xor to DT schema
dt-bindings: dma: Convert brcm,iproc-sba to DT schema
dmaengine: nbpfaxi: Add missing check after DMA map
dmaengine: mv_xor: Fix missing check after DMA map and missing unmap
dt-bindings: dma: qcom,gpi: document the Milos GPI DMA Engine
dmaengine: idxd: Remove __packed from structures
dmaengine: ti: Do not enable by default during compile testing
dmaengine: sh: Do not enable SH_DMAE_BASE by default during compile testing
dmaengine: idxd: Fix warning for deadcode.deadstore
dmaengine: mmp: Fix again Wvoid-pointer-to-enum-cast warning
dmaengine: fsl-qdma: Add missing fsl_qdma_format kerneldoc
dmaengine: qcom: gpi: Drop unused gpi_write_reg_field()
dmaengine: fsl-dpaa2-qdma: Drop unused mc_enc()
dmaengine: dw-edma: Drop unused dchan2dev() and chan2dev()
dmaengine: stm32: Don't use %pK through printk
dmaengine: stm32-dma: configure next sg only if there are more than 2 sgs
dmaengine: sun4i: Simplify error handling in probe()
dt-bindings: dma: qcom,gpi: Document the sc8280xp GPI DMA engine
...
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git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Support & Features:
- Add extensive support for the Analog Devices ADP5589 I/O expander,
including core MFD, GPIO, PWM, and a new keypad matrix input
driver. This also adds support for handling various events
including GPI, keypad, reset and unlock ev ents
- Add support for the TI TPS652G1 PMIC, a stripped-down version of
the TPS65224, including core MFD, PFSM, pinctrl, and GPIO support
- Add support for the Apple Silicon System Management Controller
(SMC), including the core MFD driver which handles the RTKit-based
protocol, a new GPIO driver for PMU GPIOs, and a new
reboot/power-off driver.
Improvements & Fixes:
- Dynamically add ADP5585 sub-devices based on device tree properties
- Move ADP5585 oscillator control from the child PWM driver to the
main MFD driver to better handle shared resources
- Add support for a hardware reset pin and VDD regulator to the
ADP5585 driver
- Update the TPS65219 MFD cell's GPIO compatible string for the
TPS65214 to reflect hardware capabilities correctly
- Separate the ChromeOS EC charge-control probing from the USB-PD
subsystem, allowing it to probe independently based on the
dedicated EC_FEATURE_CHARGER
- Fix an interrupt naming typo in the MT6370 driver
- Fix RK806 PMIC reset behavior by allowing the reset mode to be
customized via a new device tree property
- Fix AXP20X regulator cell ID conflicts for secondary PMICs on
boards without an IRQ line connected
- Fix MT6397 keypad sub-device creation to use specific names instead
of a generic one, ensuring correct driver binding
- Fix a build warning in the stm32-timers driver by adding a missing
include for export.h.
Cleanups & Refactoring:
- Refactor the ADP5585 driver to simplify how regmap defaults are
handled, making it easier to add new chip variants
- Introduce per-chip register map structures for the ADP5585/ADP5589
family to handle differences between the devices
- Convert several drivers to use dev_fwnode() instead of
of_fwnode_handle()
- Make various static structures const in the cs40l50, rohm-bd71828,
tps65219, and twl6040 drivers
- Remove redundant pm_runtime_mark_last_busy() calls from several
drivers
- Alphabetize Kconfig entries for Cirrus Logic and Maxim drivers
- Remove unused fields from the 'tps65219' struct
- Update several MFD-related headers to follow the 'Include What You
Use' (IWYU) principle.
Removals:
- Remove the old, platform-data-based adp5589-keys input driver,
which is now superseded by the new MFD-based adp5585-keys driver
- Remove the unused twl6030_mmc_card_detect() functions and
associated header declarations
- Remove the now unused pcf50633/core.h header file
- Remove the fsl,imx8qxp-csr device tree binding, which was being
used incorrectly.
Device Tree Bindings Updates:
- Add support for the Analog Devices ADP5589 I/O expander to the
adi,adp5585.yaml binding
- Add new properties to the adi,adp5585.yaml binding for input
events, including keypad pins, unlock events, and reset events
- Add a reset-gpios property to the adi,adp5585.yaml binding
- Add the TI TPS652G1 PMIC to the ti,tps6594.yaml binding
- Add new bindings for the Apple Mac System Management Controller
(SMC) and its sub-devices: apple,smc.yaml, apple,smc-gpio.yaml, and
apple,smc-reboot.yaml
- Convert the Freescale MXS LRADC binding (mxs-lradc) to YAML schema
format
- Convert and combine the NXP LPC1850 CREG, DMAMUX, and USB OTG PHY
bindings into a single YAML schema file
- Convert the TI TPS65910 binding to YAML schema format
- Add a comment to the samsung,s2mps11.yaml binding to clarify the
use of 'oneOf' for interrupt properties
- Add the rockchip,reset-mode property to the rockchip,rk806.yaml
binding to allow customization of the PMIC's reset behavior"
* tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (28 commits)
mfd: dt-bindings: Convert TPS65910 to DT schema
mfd: Minor Cirrus/Maxim Kconfig order fixes
mfd: Remove redundant pm_runtime_mark_last_busy() calls
mfd: mt6397: Do not use generic name for keypad sub-devices
mfd: axp20x: Set explicit ID for regulator cell if no IRQ line is present
mfd: mt6370: Fix the interrupt naming typo
mfd: rk8xx-core: Allow to customize RK806 reset mode
dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
mfd: syscon: atmel-smc: Don't use "proxy" headers
mfd: madera: Don't use "proxy" headers
mfd: wm8350-core: Don't use "proxy" headers
dt-bindings: mfd: samsung,s2mps11: Add comment about interrupts properties
mfd: davinci_voicecodec: Don't use "proxy" headers
mfd: pcf50633: Remove the header file core.h
mfd: tps65219: Remove another unused field from 'struct tps65219'
mfd: tps65219: Remove an unused field from 'struct tps65219'
mfd: tps65219: Constify struct regmap_irq_sub_irq_map and tps65219_chip_data
mfd: rohm-bd71828: Constify some structures
dt-bindings: mfd: fsl,imx8qxp-csr: Remove binding documentation
mfd: axp20x: Set explicit ID for AXP313 regulator
...
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phy-lpc18xx-usb-otg to YAML format
Combine the following separate plain text based bindings to YAML:
lpc1850-creg-clk.txt
pc1850-dmamux.txt
phy-lpc18xx-usb-otg.txt
Additional changes:
- remove label in example.
- remove dmamux consumer in example.
- remove clock consumer in example.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250602143612.943516-1-Frank.Li@nxp.com
Signed-off-by: Lee Jones <lee@kernel.org>
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Allow interrupt-names for fsl,imx23-dma-apbx and keep the same restriction
for others.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250523213252.582366-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Convert the Marvell Orion XOR engine binding to schema.
The "clocks" property is optional for some platforms (though not
distinguished by compatble). The child node names used are 'channel' or
'xor'.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250703155912.1713518-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Convert the Broadcom SBA RAID engine binding to schema. It is a straight
forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250702222616.2760974-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document the GPI DMA Engine on the Milos SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-9-e8f9a789505b@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document the compatible string used for the GPCDMA controller on
Tegra264.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250507143802.1230919-2-thierry.reding@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Document the GPI DMA engine on the sc8280xp platform.
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250617090032.1487382-2-mitltlatltl@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The DMA IP of Sophgo CV18XX/SG200X is based on a DW AXI CORE, with
an additional channel remap register located in the top system control
area. The DMA channel is exclusive to each core.
In addition, the DMA multiplexer is a subdevice of system controller,
so this binding only contains necessary properties for the multiplexer
itself.
Add the dmamux binding for CV18XX/SG200X series SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250611081000.1187374-2-inochiama@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"A fairly small update for the dmaengine subsystem. This has a new ARM
dmaengine driver and couple of new device support and few driver
changes:
New support:
- Renesas RZ/V2H(P) dma support for r9a09g057
- Arm DMA-350 driver
- Tegra Tegra264 ADMA support
Updates:
- AMD ptdma driver code removal and optimizations
- Freescale edma error interrupt handler support"
* tag 'dmaengine-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (27 commits)
dmaengine: idxd: Remove unused pointer and macro
arm64: dts: renesas: r9a09g057: Add DMAC nodes
dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
dmaengine: sh: rz-dmac: Allow for multiple DMACs
irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req()
dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H
dmaengine: idxd: Narrow the restriction on BATCH to ver. 1 only
dmaengine: ti: Add NULL check in udma_probe()
fsldma: Set correct dma_mask based on hw capability
dmaengine: idxd: Check availability of workqueue allocated by idxd wq driver before using
dmaengine: xilinx_dma: Set dma_device directions
dmaengine: tegra210-adma: Add Tegra264 support
dt-bindings: Document Tegra264 ADMA support
dmaengine: dw-edma: Add HDMA NATIVE map check
dmaegnine: fsl-edma: add edma error interrupt handler
dt-bindings: dma: fsl-edma: increase maxItems of interrupts and interrupt-names
dmaengine: ARM_DMA350 should depend on ARM/ARM64
dt-bindings: dma: qcom,bam: Document dma-coherent property
dmaengine: Add Arm DMA-350 driver
...
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Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
Renesas RZ/G2L family of SoCs, but there are some differences:
* It only uses one register area
* It only uses one clock
* It only uses one reset
* Instead of using MID/IRD it uses REQ No
* It is connected to the Interrupt Control Unit (ICU)
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250423143422.3747702-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Make sure we don't allow for the clocks, clock-names, resets,
reset-names. and power-domains properties for the Renesas
RZ/A1H SoC because its DMAC doesn't have clocks, resets,
and power domains.
Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250423143422.3747702-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add Tegra264 ADMA support to the device tree bindings documentation.
The Tegra264 ADMA hardware supports 64 DMA channels and requires
specific register configurations.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250512050010.1025259-2-sheetal@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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schema
Update text binding to YAML.
Changes during conversion:
- Add a fallback for "nvidia,tegra30-apbdma" as it is
compatible with the IP core on "nvidia,tegra20-apbdma".
- Update examples and include appropriate file directives to resolve
errors identified by `dt_binding_check` and `dtbs_check`.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250507-nvidea-dma-v4-2-6161a8de376f@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The edma controller support optional error interrupt, so update interrupts
and interrupt-names's maxItems.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250407-edma_err-v2-1-9d7e5b77fcc4@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Qualcomm BAM DMA controller has DMA-coherent support so define it in the
properties section.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com>
Link: https://lore.kernel.org/r/20250423063054.28795-3-quic_kaushalk@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Arm CoreLink DMA-350 is a pleasantly straightforward DMA controller
which, although highly configurable, lends itself to a simple binding
thanks to plenty of self-describing ID registers.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/15830b2a8ff9721e364f30f93ea3993139b0103b.1741780808.git.robin.murphy@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"The dmaengine subsystem updates for this cycle consist of a new driver
(Microchip) along with couple of yaml binding conversions, core api
updates and bunch of driver updates etc.
New HW support:
- Microchip sama7d65 dma controller
- Yaml conversion of atmel dma binding and Freescale Elo DMA
Controller binding
Core:
- Remove device_prep_dma_imm_data() API as users are removed
- Reduce scope of some less frequently used DMA request channel APIs
with aim to cleanup these in future
Updates:
- Drop Fenghua Yu from idxd maintainers, as he changed jobs
- AMD ptdma support for multiqueue and ae4dma deprecated PCI IDs
removal"
* tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (29 commits)
dmaengine: ptdma: Utilize the AE4DMA engine's multi-queue functionality
dmaengine: ae4dma: Use the MSI count and its corresponding IRQ number
dmaengine: ae4dma: Remove deprecated PCI IDs
dmaengine: Remove device_prep_dma_imm_data from struct dma_device
dmaengine: ti: edma: support sw triggered chans in of_edma_xlate()
dmaengine: ti: k3-udma: Enable second resource range for BCDMA and PKTDMA
dmaengine: fsl-edma: free irq correctly in remove path
dmaengine: fsl-edma: cleanup chan after dma_async_device_unregister
dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
dmaengine: dmatest: Fix dmatest waiting less when interrupted
dt-bindings: dma: Convert fsl,elo*-dma to YAML
dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
dmaengine: Fix typo in comment
dmaengine: ti: k3-udma-glue: Drop skip_fdq argument from k3_udma_glue_reset_rx_chn
dmaengine: bcm2835-dma: fix warning when CONFIG_PM=n
dt-bindings: dma: fsl,edma: Add i.MX94 support
dt-bindings: dma: atmel: add microchip,sama7d65-dma
dmaengine: img-mdc: remove incorrect of_match_ptr annotation
dmaengine: idxd: Delete unnecessary NULL check
dmaengine: pxa: Enable compile test
...
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A RISC-V platform can have both DMA coherent/noncoherent devices.
Since the RISC-V architecture is marked coherent, devices should
be marked as noncoherent when coherent devices exist.
Add dma-noncoherent property for snps,dw-axi-dmac device. It will
be used on SG2044, and it has other coherent devices.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250303065649.937233-1-inochiama@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The devicetree bindings for Freescale DMA engines have so far existed as
a text file. This patch converts them to YAML, and specifies all the
compatible strings currently in use in arch/powerpc/boot/dts.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250308-ppcyaml-dma-v4-1-20392ea81ec6@posteo.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add compatible string for all i.MX8 chips, which is backward compatible
with i.MX28. Set it to fall back to "fsl,imx28-dma-apbh".
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250307215100.3257649-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add support for the i.MX94 DMA controllers. The SoC includes two DMA
controllers: one compatible with i.MX93 eDMA3 and another compatible with
i.MX95 eDMA5.
Add compatible string "fsl,imx94-edma3" with fallback to "fsl,imx93-edma3".
Add compatible string "fsl,imx94-edma5" with fallback to "fsl,imx95-edma5".
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250221222153.405285-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add microchip,sama7d65-dma compatible string to DT bindings
documentation.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/8b69f0c6d8955790edcdbe5d1e205b43dedb99ff.1739555984.git.Ryan.Wanner@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Firmware contants do not fit the purpose of bindings because they are not
independent IDs for abstractions. They are more or less just contants which
better to wire via header with DT which is using it.
That's why add deprecated message to dt binding header and also update
existing dt bindings not to use macros from the header and replace them by
it's value. Actually value is not relevant because it is only example.
The similar changes have been done by commit 9d9292576810 ("dt-bindings:
pinctrl: samsung: deprecate header with register constants").
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2a6f0229522327939e6893565e540b75f854a37b.1738600745.git.michal.simek@amd.com
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Add a description, required properties, appropriate compatibles and
missing properties like clocks and clock-names which are not defined in
the text binding for all the SoCs that are supported by microchip.
Update the text binding name `atmel-dma.txt` to
`atmel,at91sam9g45-dma.yaml` for the files which reference to
`atmel-dma.txt`. Drop Tudor name from maintainers.
Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250203-test-v4-1-a9ec3eded1c7@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Convert old text based binding to json schema.
Changes during conversion:
- Add the required properties `clock` and `clock-names`, which were
missing in the original binding.
- Add a fallback for `microchip,sam9x7-dma` and `microchip,sam9x60-dma`
as they are compatible with the dma IP core on `atmel,sama5d4-dma`.
- Update examples and include appropriate file directives to resolve
errors identified by `dt_binding_check` and `dtbs_check`.
Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241205-xdma-v1-1-76a4a44670b5@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The dma-cell values for the stm32-dmamux are used to craft the DMA spec
for the actual controller. These values are currently undocumented
leaving the user to reverse engineer the driver in order to determine
their meaning. Add a basic description, while avoiding duplicating
information by pointing the user to the associated DMA docs that
describe the fields in depth.
Signed-off-by: Ken Sloat <ksloat@cornersoftsolutions.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20241206115018.1155149-1-ksloat@cornersoftsolutions.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Deprecate the adi,channels node in the adi,axi-dmac binding. Prior to
IP version 4.3.a, this information was required. Since then, there are
memory-mapped registers that can be read to get the same information.
Acked-by: Nuno Sa <nuno.sa@analog.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-2-7b994710c43f@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Convert the AXI DMAC bindings from .txt to .yaml.
Acked-by: Nuno Sa <nuno.sa@analog.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-1-7b994710c43f@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Multiple ADMA Channel page hardware support has been added from
TEGRA186 and onwards. Update the DT binding to use any of the
ADMA channel page address space region.
Signed-off-by: Mohan Kumar D <mkumard@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241217074358.340180-2-mkumard@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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J722S CSI BCDMA is similar to J721S2 CSI BCDMA and supports both RX and TX
channels but has a different PSIL thread base ID which is currently
handled in k3-udma driver. Add an entry for J722S CSIRX BCDMA.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241127101627.617537-2-vaishnav.a@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Introduce the compatible strings 'nxp,s32g2-edma' and 'nxp,s32g3-edma' to
enable the support for the eDMAv3 present on S32G2/S32G3 platforms.
The S32G2/S32G3 eDMA architecture features 32 DMA channels. Each of the
two eDMA instances is integrated with two DMAMUX blocks.
Another particularity of these SoCs is that the interrupts are shared
between channels in the following way:
- DMA Channels 0-15 share the 'tx-0-15' interrupt
- DMA Channels 16-31 share the 'tx-16-31' interrupt
- all channels share the 'err' interrupt
Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241219102415.1208328-4-larisa.grigore@oss.nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document the GPI DMA engine on the sm8750 platform.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241021230500.2632527-1-quic_molvera@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add compatible string for Allwinner suniv F1C100s DMA.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[ csokas.bence: Reimplemented Mesih Kilinc's binding in YAML ]
Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
Link: https://lore.kernel.org/r/20241122161128.2619172-4-csokas.bence@prolan.hu
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add a compatible for the GPI DMA controller on SA8775P.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241108-topic-sa8775_dma2-v1-1-1d3b0d08d153@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document compatible for GPI DMA controller on QCS8300 platform.
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241112041252.351266-1-quic_vdadhani@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document compatible for GPI DMA controller on QCS615 platform.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20241115092854.1877369-1-quic_vdadhani@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"New hardware support:
- Qualcomm SAR2130P GPI dma support
- Sifive PIC64GX pdma support
- Rcar r7s72100 support and associated updates
Updates:
- STM32 DMA3 updates for packing/unpacking mode and prevention of
additional xfers
- Simplification of devm_acpi_dma_controller_register() and associate
cleanup including headers
- loongson prefix renames
- Switch back to platform_driver::remove() subsystem update"
* tag 'dmaengine-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
dmaengine: loongson2-apb: Rename the prefix ls2x to loongson2
dt-bindings: dma: sifive pdma: Add PIC64GX to compatibles
dmaengine: fix typo in the comment
dmaengine: stm32-dma3: clamp AXI burst using match data
dmaengine: stm32-dma3: prevent LL refactoring thanks to DT configuration
dt-bindings: dma: stm32-dma3: prevent additional transfers
dmaengine: stm32-dma3: refactor HW linked-list to optimize memory accesses
dmaengine: stm32-dma3: prevent pack/unpack thanks to DT configuration
dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode
dmaengine: idxd: Move DSA/IAA device IDs to IDXD driver
dt-bindings: dma: qcom,gpi: Add SAR2130P compatible
dmaengine: Switch back to struct platform_driver::remove()
dmaengine: ep93xx: Fix unsigned compared against 0
dmaengine: acpi: Clean up headers
dmaengine: acpi: Simplify devm_acpi_dma_controller_register()
dmaengine: acpi: Drop unused devm_acpi_dma_controller_free()
dmaengine: sh: rz-dmac: add r7s72100 support
dt-bindings: dma: rz-dmac: Document RZ/A1H SoC
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PIC64GX is compatible as out of order DMA capable, just like the MPFS
version, therefore we add it with microchip,mpfs-pdma as a fallback
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240930095449.1813195-10-pierre-henry.moussay@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Some devices require a single transfer. For example, reading FMC ECC status
registers does not support multiple transfers.
Add the possibility to prevent additional transfers, by setting bit 17 of
the 'DMA transfer requirements' bit mask.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-4-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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When source data width/burst and destination data width/burst are
different, data are packed or unpacked in DMA3 channel FIFO.
Data are pushed out from DMA3 channel FIFO when the destination burst
length (= data width * burst) is reached.
If the channel is stopped before the transfer end, and if some bytes are
packed/unpacked in the DMA3 channel FIFO, these bytes are lost.
Indeed, DMA3 channel FIFO has no flush capability, only reset.
To avoid potential bytes lost, pack/unpack must be prevented by setting
memory data width/burst equal to peripheral data width/burst.
Memory accesses will be penalized. But it is the only way to avoid bytes
lost.
Some devices (e.g. cyclic RX like UART) need this, so add the possibility
to prevent pack/unpack feature, by setting bit 16 of the 'DMA transfer
requirements' bit mask.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-1-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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