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path: root/arch/arc/mm/cache.c
AgeCommit message (Expand)AuthorLines
2017-09-01ARC: mm: Decouple RAM base address from kernel link addressEugeniy Paltsev-1/+1
2017-09-01ARCv2: IOC: Tighten up the contraints (specifically base / size alignment)Eugeniy Paltsev-8/+19
2017-08-30ARCv2: SLC: provide a line based flush routine for debuggingVineet Gupta-1/+53
2017-08-28ARC: set boot print log level to PR_INFONoam Camus-1/+1
2017-08-04ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoCVineet Gupta-6/+28
2017-08-04ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addressesAlexey Brodkin-2/+11
2017-08-04ARCv2: SLC: Make sure busy bit is set properly for region opsAlexey Brodkin-0/+3
2017-05-02ARCv2: mm: Merge 2 updates to DC_CTRL for region flushVineet Gupta-14/+32
2017-05-02ARCv2: mm: Implement cache region flush operationsVineet Gupta-0/+68
2017-05-02ARC: mm: Move full_page computation into cache version agnostic wrapperVineet Gupta-13/+12
2017-03-30ARCv2: SLC: Make sure busy bit is set properly on SLC flushingAlexey Brodkin-0/+3
2017-01-18ARC: Revert "ARC: mm: IOC: Don't enable IOC by default"Vineet Gupta-1/+1
2017-01-18ARC: mm: split arc_cache_init to allow __init reaping of bulkVineet Gupta-14/+19
2017-01-18ARCv2: IOC: Use actual memory size to setup aperture sizeVineet Gupta-2/+10
2017-01-18ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruptionVineet Gupta-0/+46
2017-01-18ARCv2: IOC: refactor the IOC and SLC operations into own functionsVineet Gupta-21/+47
2017-01-04ARC: mmu: clarify the MMUv3 programming modelVineet Gupta-1/+5
2016-12-19ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcacheVineet Gupta-4/+9
2016-12-19ARC: mm: No need to save cache version in @cpuinfoVineet Gupta-11/+4
2016-11-28ARC: mm: IOC: Don't enable IOC by defaultVineet Gupta-1/+1
2016-10-28ARCv2: boot log: print IOC exists as well as enabled statusVineet Gupta-6/+3
2016-10-24ARCv2: IOC: use @ioc_enable not @ioc_exist where intendedVineet Gupta-4/+6
2016-09-30ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 coresVineet Gupta-5/+18
2016-08-10ARC: Elide redundant setup of DMA callbacksVineet Gupta-0/+9
2016-05-30Fix typosAndrea Gelmini-3/+3
2016-04-04mm, fs: get rid of PAGE_CACHE_* and page_cache_{get,release} macrosKirill A. Shutemov-1/+1
2016-03-19ARCv2: ioremap: Support dynamic peripheral address spaceVineet Gupta-0/+7
2016-03-19ARC: dma: ioremap: use phys_addr_t consistenctly in code pathsVineet Gupta-15/+15
2016-03-11ARC: Fix misspellings in comments.Adam Buchbinder-1/+1
2016-01-15mm: differentiate page_mapped() from page_mapcount() for compound pagesKirill A. Shutemov-2/+2
2015-10-29ARC: mm: PAE40 supportVineet Gupta-4/+40
2015-10-28ARC: mm: PAE40: switch to using phys_addr_t for physical addressesVineet Gupta-13/+13
2015-10-28ARC: mm: preps ahead of HIGHMEM supportVineet Gupta-5/+11
2015-10-17ARC: boot log: move helper macros to header for reuseVineet Gupta-3/+2
2015-08-21ARC: Eliminate some ARCv2 specific code for ARCompact buildVineet Gupta-26/+32
2015-08-20ARCv2: IOC: Allow boot time disableAlexey Brodkin-3/+4
2015-08-20ARCv2: SLC: Allow boot time disableVineet Gupta-2/+19
2015-08-20ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin-16/+98
2015-07-06ARCv2: guard SLC DMA ops with spinlockAlexey Brodkin-2/+10
2015-06-25ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)Vineet Gupta-2/+62
2015-06-22ARCv2: MMUv4: support aliasing icache configVineet Gupta-1/+13
2015-06-22ARCv2: MMUv4: cache programming model changesVineet Gupta-15/+97
2015-06-19ARC: untangle cache flush loopVineet Gupta-25/+55
2015-06-19ARC: cacheflush: No need to retain DC_CTRL from __before_dc_op()Vineet Gupta-20/+19
2015-06-19ARC: cacheflush: move some code around, delete old commentsVineet Gupta-165/+102
2015-06-19ARC: mm/cache_arc700.c -> mm/cache.cVineet Gupta-0/+723
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