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2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner-12/+1
2019-05-01arm64: Fix size of __early_cpu_boot_statusArun KS-1/+1
2019-04-05arm64: Use defines instead of magic numbersAlexandru Elisei-5/+5
2019-02-20arm64: Relax GIC version check during early bootVladimir Murzin-2/+1
2019-01-10arm64: kpti: Avoid rewriting early page tables when KASLR is enabledWill Deacon-0/+1
2018-12-13arm64/kvm: consistently handle host HCR_EL2 flagsMark Rutland-3/+2
2018-12-10Merge branch 'for-next/kexec' into aarch64/for-next/coreWill Deacon-1/+2
2018-12-10arm64: smp: Rework early feature mismatched detectionWill Deacon-8/+4
2018-12-10arm64: Kconfig: Re-jig CONFIG options for 52-bit VAWill Deacon-2/+2
2018-12-10arm64: mm: introduce 52-bit userspace supportSteve Capper-0/+13
2018-12-10arm64: mm: Prevent mismatched 52-bit VA supportSteve Capper-0/+26
2018-12-10arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGDSteve Capper-0/+1
2018-12-06arm64: add image head flag definitionsAKASHI Takahiro-1/+2
2018-09-25arm64/mm: move runtime pgds to rodataJun Yao-5/+7
2018-09-25arm64/mm: Separate boot-time page tables from swapper_pg_dirJun Yao-5/+5
2018-09-25arm64/mm: Pass ttbr1 as a parameter to __enable_mmu()Jun Yao-9/+11
2018-02-26arm64/kvm: Prohibit guest LOR accessesMark Rutland-0/+7
2018-02-06arm64: idmap: Use "awx" flags for .idmap.text .pushsection directivesWill Deacon-1/+1
2018-02-06arm64: assembler: Align phys_to_pte with pte_to_physWill Deacon-22/+2
2018-02-06arm64: assembler: Change order of macro arguments in phys_to_ttbrWill Deacon-2/+2
2018-02-06arm64: Add software workaround for Falkor erratum 1041Shanker Donthineni-0/+1
2018-01-16arm64: sysreg: Move to use definitions for all the SCTLR bitsJames Morse-10/+3
2018-01-14arm64: Extend early page table code to allow for larger kernelsSteve Capper-38/+106
2017-12-22arm64: allow ID map to be extended to 52 bitsKristina Martsenko-31/+45
2017-12-22arm64: handle 52-bit physical addresses in page table entriesKristina Martsenko-1/+1
2017-12-22arm64: head.S: handle 52-bit PAs in PTEs in early page table setupKristina Martsenko-9/+31
2017-12-22arm64: handle 52-bit addresses in TTBRKristina Martsenko-2/+4
2017-11-03arm64/sve: Low-level CPU setupDave Martin-1/+12
2017-10-18arm64: head: Init PMSCR_EL2.{PA,PCT} when entered at EL2 without VHEWill Deacon-5/+12
2017-09-27arm64: Make sure SPsel is always setMarc Zyngier-0/+1
2017-09-05Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds-9/+13
2017-08-22arm64: kaslr: ignore modulo offset when validating virtual displacementArd Biesheuvel-1/+0
2017-08-09Merge branch 'arm64/exception-stack' of git://git.kernel.org/pub/scm/linux/ke...Catalin Marinas-0/+4
2017-08-09arm64: unwind: reference pt_regs via embedded stack frameArd Biesheuvel-0/+4
2017-08-09arm64: Convert __inval_cache_range() to area-basedRobin Murphy-9/+9
2017-04-04Merge branch 'arm64/common-sysreg' of git://git.kernel.org/pub/scm/linux/kern...Catalin Marinas-4/+4
2017-04-04arm64: efi: clean up Image header after PE header has been split offArd Biesheuvel-9/+3
2017-04-04arm64: efi: move EFI header and related data to a separate .S fileArd Biesheuvel-147/+3
2017-03-22arm64: move !VHE work to end of el2_setupMark Rutland-20/+17
2017-03-22arm64: reduce el2_setup branchingMark Rutland-8/+7
2017-03-09arm64: sysreg: subsume GICv3 sysreg definitionsMark Rutland-4/+4
2017-02-09arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2Will Deacon-4/+15
2017-02-03efi: arm64: Add vmlinux debug link to the Image binaryArd Biesheuvel-1/+46
2017-01-17arm64: head.S: avoid open-coded adr_lMark Rutland-2/+1
2017-01-10arm64: head.S: fix up stale commentsMark Rutland-2/+2
2016-11-29arm64: head.S: Fix CNTHCTL_EL2 access on VHE systemJintack-1/+12
2016-11-21arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1Catalin Marinas-3/+3
2016-11-11arm64: split thread_info from task stackMark Rutland-5/+6
2016-10-17arm64: kernel: Init MDCR_EL2 even in the absence of a PMUMarc Zyngier-1/+2
2016-09-02arm64: head.S: document the use of callee saved registersArd Biesheuvel-0/+10
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