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Pull SoC devicetree updates from Arnd Bergmann:
"A number of SoC platforms are adding modernized variants of their
already supported chips time, with a total of 12 new SoCs, and two
older SoC getting removed:
- Qualcomm Glymur is a compute SoC using 18 Oryon-2 CPU cores
- Qualcomm Mahua is a variant of Glymur with only 12 CPU cores, but
largely identical.
- Qualcomm Eliza is an embeded platform for mobile phone (SM7750) and
IOT (QC7790S/M) workloads
- Qualcomm IPQ5210 is a wireless networking SoC using Cortex-A53
cores
- Qualcomm apq8084 and ipq806x had only rudimentary support but no
actual products using them, so they are now gone.
- Axis ARTPEC-9 is a follow-up to the ARTPEC-8 embedded SoC, using
the Samsung SoC platform but now with Cortex-A55 cores
- ARM Zena is a virtual platform in FVP using Cortex-A720AE cores,
with additional versions planned to be merged in the future.
- ARM corstone-1000-a320 is a reference platform for IOT, using
low-end Cortex-A320 cores
- Microchip LAN9691 is an updated 64-bit variant of the arm32 lan966x
series of networking SoCs
- Microchip PIC64GX is an embedded RISC-V chip using SIFIVE U54 CPU
cores
- Rockchip RV1103B is the low-end 32-bit single-core vision processor
- Renesas RZ/G3L (r9a08g046) is an industrial embedded chip using
Cortex-A55 cores, similar to the G3E and G3S variants we already
supported.
- NXP S32N79 is an automotive SoC using Cortex-A78AE cores, a
significant upgrade from the older S32V and S32G series
These all come with at least one reference board or an initial product
using these, in total there are 67 newly added boards. The ones for
already supported SoCs are:
- Two more Aspeed BMC based boards
- Three older tablets based on 32-bit OMAP4 and Exynos5 SoCs
- One Set-top-box based on Allwinner H6
- 22 additional industrial/embedded boards using 64-bit NXP i.MX8M or
i.MX9 SoCs
- 20 Qualcomm SoC based machines across all possible markets:
workstation, gaming, laptop, phone, networking, reference, ...
- Three more Rockchips rk35xx based boards
- Four variants of the Toradex Verdin using TI AM62
Other notable bits are:
- A cleanup for the 32-bit Tegra paz00 board moved the last board
specific code on Tegra into equivalent dts syntax.
- There continues to be a significant number of fixes for static
checking of dtc syntax, but it feels like this is slowing down,
hopefully getting into a state where most known issues are
addressed
- Additional hardware support for many existing boards across SoC
families, notably Qualcomm, Broadcom, i.MX2, i.MX6, Rockchips,
STM32, Mediatek, Tegra, TI and Microchip"
* tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (841 commits)
arm64: dts: ti: k3: Use memory-region-names for r5f
ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boards
ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdif
ARM: dts: imx25: rename node name tcq to touchscreen
ARM: dts: imx: b850v3: Disable unused usdhc4
ARM: dts: imx: b850v3: Define GPIO line names
ARM: dts: imx: b850v3: Use alphabetical sorting
ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warning
ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100Mbps
ARM: dts: imx7ulp: Add CPU clock and OPP table support
ARM: dts: imx7-mba7: Deassert BOOT_EN after boot
ARM: dts: tqma7: add boot phase properties
ARM: dts: imx7s: add boot phase properties
ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems
ARM: dts: mba6ulx: add boot phase properties
ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties
ARM: dts: imx6ul/imx6ull: add boot phase properties
ARM: dts: imx6qdl-mba6: add boot phase properties
ARM: dts: imx6qdl-tqma6: add boot phase properties
ARM: dts: imx6qdl: add boot phase properties
...
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ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V devicetrees for v7.1
Generic:
Add binding coverage for Supm.
Microchip:
Add support for the picgx64 and its curiosity board. This is a PolarFire
SoC without the FPGA.
Add the missing tsu_clk for ptp on the macb on PolarFire SoC and resolve
a long-running problem with gpio interrupts being incorrectly described
on the platform.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC
riscv: dts: microchip: add tsu clock to macb on mpfs
dt-bindings: riscv: Add Supm extension description
riscv: dts: microchip: remove POLARFIRE mention in Makefile
riscv: dts: microchip: add pic64gx and its curiosity kit
dt-bindings: riscv: microchip: document the PIC64GX curiosity kit
dt-bindings: timer: sifive,clint: add pic64gx compatibility
riscv: dts: microchip: add pinctrl nodes for mpfs/icicle kit
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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into soc/dt
RISC-V SpacemiT DT changes for 7.1
For K3 SoC
- Add I2C support
- Add PMIC regulator tree
- Add ethernet support
- Add pinctrl/GPIO/Clock
- Enable full UART support
For K1 SoC
On Milk-V Jupiter
- Enable PCIe/USB on
- Enable QSPI/SPI NOR
- Enable EEPROM, LEDs
Others
- Fix PMIC supply properties
- Fix PCIe missing power regulator
* tag 'spacemit-dt-for-7.1-1' of https://github.com/spacemit-com/linux:
dts: riscv: spacemit: k3: add P1 PMIC regulator tree
dts: riscv: spacemit: k3: Add i2c nodes
riscv: dts: spacemit: enable PCIe ports on Milk-V Jupiter
riscv: dts: spacemit: enable USB 3 ports on Milk-V Jupiter
riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter
riscv: dts: spacemit: add i2c aliases on Milk-V Jupiter
riscv: dts: spacemit: add 24c04 eeprom on Milk-V Jupiter
riscv: dts: spacemit: add LEDs for Milk-V Jupiter board
riscv: dts: spacemit: Add ethernet device for K3
riscv: dts: spacemit: drop incorrect pinctrl for combo PHY
riscv: dts: spacemit: reorder phy nodes for K1
riscv: dts: spacemit: k3: add full resource to UART
riscv: dts: spacemit: k3: add GPIO support
riscv: dts: spacemit: k3: add pinctrl support
riscv: dts: spacemit: k3: add clock tree
dt-bindings: serial: 8250: spacemit: fix clock property for K3 SoC
riscv: dts: spacemit: Add 'linux,pci-domain' to PCIe nodes for K1
riscv: dts: spacemit: adapt regulator node name to preferred form
riscv: dts: spacemit: Update PMIC supply properties for BPI-F3 and Jupiter
riscv: dts: spacemit: pcie: fix missing power regulator
Signed-off-by: Linus Walleij <linusw@kernel.org>
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There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used
to ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct
mode", as they provide an exclusive connection from a GPIO to the PLIC.
The 3 remaining interrupts are used to mux the interrupts which do not
have a exclusive connection, one for each GPIO controller.
The mux was overlooked when the bindings and driver were originally
written for the GPIO controllers on Polarfire SoC, and the interrupts
property in the GPIO nodes used to try and convey what the mapping was.
Instead, the mux should be a device in its own right, and the GPIO
controllers should be connected to it, rather than to the PLIC.
Now that a binding exists for that mux, fix the inaccurate description
of the interrupt controller hierarchy.
GPIO controllers 0 and 1 do not have all 32 possible GPIO lines, so
ngpios needs to be set to match the number of lines/interrupts.
The m100pfsevp has conflicting interrupt mappings for controllers 0 and
2, as they cannot both be using an interrupt in "direct mode" at the
same time, so the default replaces this impossible configuration.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add the P1 PMIC's regulator topology tree for pico-itx board.
Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-9c6b374470c6@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of
i2c3 is reserved for secure domain, and not available from Linux. The
controller of i2c7 simply doesn't exist from hardware perspective, as
vendor directly name the i2c controller used for PMIC as i2c8.
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-2119c0918868@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Enable the two PCIe controller along with and their associated PHY. They
are routed to the M.2 M-key connector and to the PCIe x8 slot.
Add an always-on regulator sourcing 3.3V from the DC-IN input, to power
the PCIe ports.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326183745.1370642-7-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Enable the DWC3 USB 3.0 controller (USB#2 port in the K1 datasheet) and
its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the
Milk-V Jupiter board.
The board uses a VLI VL817 hub, providing four ports. Two are routed to
the 3.0 type-A connectors, and two to the F_USB3 front USB header. The
hub requires two separate 5V power supplies: one for the hub itself and
one for the USB connectors. Add an always-on regulator sourcing 5V from
the DC-IN input, along with two GPIO-controlled fixed regulators to
manage the hub and connectors power supplies.
Note that the board also provides four USB 2.0 ports (two via type-A
connectors and two via the F_USB2 front USB header), but these are
handled by a different controller (USB#1 port in the K1 datasheet).
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326183745.1370642-6-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Add the QSPI controller node for the Milk-V Jupiter board and describe
the attached SPI NOR flash (GD25Q64E).
The flash supports a frequency up to 133MHz (80 MHz for reads), and the
SoC supports a frequency up to 104 MHz. However tests have shown that
the flash is not reliably detected above 26.5 MHz, consistent with
frequency used in the vendor kernel. Therefore, use this frequency.
The m25p,fast-read properties is taken from the vendor kernel, and the
GD25Q64E datasheet confirms tha the fast read opcodes are supported.
Add a corresponding flash partition layout, matching the layout and the
names used in the vendor U-Boot.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326183745.1370642-5-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Add i2c aliases for i2c2 and i2c8 on Milk-V Jupiter. This is useful to
keep a stable number for the /dev entries after loading the i2c-dev
module.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326183745.1370642-4-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
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The Milk-V Jupiter board includes a 24c04 eeprom on the i2c2 bus. The
eeprom contains an ONIE TLV table, which on the board I tested only
provides a product-name entry. Expose it via an onie,tlv-layout nvmem
layout.
The eeprom is marked as read-only since its contents are not supposed to
be modified.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326183745.1370642-3-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
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The Milk-V Jupiter board provides support for two LEDs through the front
panel header. The "Power LED" indicates the system is running, and the
"HDD LED" shows disk activity. Configure the corresponding LED triggers
accordingly.
Caveats:
- The LEDs are driven through a 4.7k series resistor, making them
quite faint.
- The disk activity trigger requires a storage controller on the M.2 or
PCIe interface. That said, it matches the purpose and the vendor
kernel.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326183745.1370642-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Add all ethernet device nodes for K3 SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
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The BeagleV Ahead board includes a micro HDMI connector (Type-D)
wired to the TH1520 SoC's HDMI transmitter.
Enable the display pipeline by adding the HDMI connector node,
connecting it to the HDMI controller, and activating the DPU
and HDMI nodes.
Signed-off-by: Robert Mazur <robert.mazur@imgtec.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
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In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is required for
correct rate selection.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Substitute user hidden CONFIG_ARCH_MICROCHIP_POLARFIRE by user visible
CONFIG_ARCH_MICROCHIP.
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC
prototyping board featuring a Microchip PIC64GX SoC PIC64GC-1000.
Features include:
- 1 GB DDR4 SDRAM
- Gigabit Ethernet
- microSD-card slot
note: due to issue on some board, the SDHCI is limited to HS (High
speed mode, with a clock of 50MHz and 3.3V signals).
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add pinctrl nodes to PolarFire to demonstrate their use, matching the
default configuration set by the HSS firmware for the Icicle kit's
reference design, as a demonstration of use.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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The combo PHY on the Banana Pi F3 is used for the USB 3.0 port. The high
speed differential lanes are always configured as such, and do not
require a pinctrl entry.
The existing pinctrl entry only configures PCIe secondary pins, which
are unused for USB and instead routed to the MIPI CSI1 connector.
Remove this incorrect pinctrl entry.
Fixes: 0be016a4b5d1b9 ("riscv: dts: spacemit: PCIe and PHY-related updates")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260322202502.2205755-1-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Reorder the PHY nodes of USB and PCIe to the correct positions based on
the register address. This improves the readability and maintainability
of the DT. No functional change is introduced by this reordering.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260318100000.3934516-1-amadeus@jmu.edu.cn
Signed-off-by: Yixun Lan <dlan@kernel.org>
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The manual of TH1520 contains a set of coefficients a little different
to the driver default ones.
Add them to the device tree node of PVT.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
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Lichee Pi 4A board features a HDMI Type-A connector connected to the
HDMI TX controller of TH1520 SoC.
Add a device tree node describing the connector, connect it to the HDMI
controller, and enable everything on this display pipeline.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
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T-Head TH1520 SoC contains a Verisilicon DC8200 display controller
(called DPU in manual) and a Synopsys DesignWare HDMI TX controller.
Add device tree nodes to them.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
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Previously the UART rely on external bootloader to initialize clock,
pinctrl and reset, to solve this, explicitly adding those resource in
Device Tree, so UART driver will handle them properly.
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Add GPIO node in the Device Tree, so devices are able to request GPIO
resource properly.
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-3-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices
can request pinctrl resource properly.
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-2-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Add clock support to SpacemiT K3 SoC, the clock tree consist of several
blocks which are APBC, APMU, DCIU, MPUM.
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the
'linux,pci-domain' property to assign a PCI domain number to
each of the controllers instead of assigning it randomly.
This creates a stable sysfs path, allowing userspace scripts
to reliably target specific PCIe devices (such as PCIe NICs).
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn
Signed-off-by: Yixun Lan <dlan@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
RISC-V soc fixes for v7.0-rc1
drivers:
Fix leaks in probe/init function teardown code in three drivers.
microchip:
Fix a warning introduced by a recent binding change, that made resets
required on Polarfire SoC's CAN IP.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-soc-fixes-for-v7.0-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
cache: ax45mp: Fix device node reference leak in ax45mp_cache_init()
cache: starfive: fix device node leak in starlink_cache_init()
riscv: dts: microchip: add can resets to mpfs
soc: microchip: mpfs: Fix memory leak in mpfs_sys_controller_probe()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The preferred node name for fixed-regulators has changed to pattern [1]:
'^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$'
Adjust all SpacemiT DT regulator node names to fix this.
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1]
Link: https://lore.kernel.org/r/20260226-02-k1-regulator-names-v1-1-e87695d50159@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Use per-regulator supply names in pmic "spacemit,p1" node to specify
each board's power tree topology and match the updated dt-binding.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
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The PCIe port require 3.3v power regulator for device to work properly, So
explicitly add it to fix the DT warning:
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dtb: pcie@ca400000 (spacemit,k1-pcie): pcie@0: 'vpcie3v3-supply' is a required property
from schema $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml
Fixes: 0be016a4b5d1 ("riscv: dts: spacemit: PCIe and PHY-related updates")
Reported-by: Conor Dooley <conor@kernel.org>
Link: https://lore.kernel.org/r/20260226-k1-pcie-fix-pwr-v1-1-94b493cd27e5@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Pull SoC devicetree updates from Arnd Bergmann:
"There are a handful of new SoCs this time, all of these are more or
less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is entirely
unrelated with the similarly named Texas Instruments K3 chip family
that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built on newer
Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high performance
Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400, ST
spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
am3703/am3715. All of these could be restored easily if a new board
gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI based
firmware.
A relatively small number of 43 boards get added this time, and almost
all of them for arm64. Aside from the reference boards for the newly
added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4, CIX
sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards getting
a warning-free dtc build, and the usual work on adding support for
more hardware on the previously added machines"
* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
dt-bindings: intel: Add Agilex eMMC support
arm64: dts: socfpga: agilex: add emmc support
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
ARM: dts: socfpga: fix dtbs_check warning for fpga-region
ARM: dts: socfpga: add #address-cells and #size-cells for sram node
dt-bindings: altera: document syscon as fallback for sys-mgr
arm64: dts: altera: Use lowercase hex
dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
arm64: dts: socfpga: agilex5: add support for modular board
dt-bindings: intel: Add Agilex5 SoCFPGA modular board
arm64: dts: socfpga: agilex5: Add dma-coherent property
arm64: dts: realtek: Add Kent SoC and EVB device trees
dt-bindings: arm: realtek: Add Kent Soc family compatibles
ARM: dts: samsung: Drop s3c6400.dtsi
ARM: dts: nuvoton: Minor whitespace cleanup
MAINTAINERS: Add Falcon DB
arm64: dts: a7k: add COM Express boards
ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
arm64: dts: rockchip: Fix rk3588 PCIe range mappings
...
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The can IP on PolarFire SoC requires the use of the blocks reset
during normal operation, and the property is therefore required by the
binding, causing a warning on the m100pfsevp board where it is default
enabled:
mpfs-m100pfsevp.dtb: can@2010c000 (microchip,mpfs-can): 'resets' is a required property
Add the reset to both can nodes.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.20 (or v7.0)
Anlogic:
Minor change to the extension information, to add the "b" extension
that's a catch-all for 3 of the extensions already in the dts.
Starfive:
Append the jh7110 compatible to jh7110s devicetrees, as that will enable
OpenSBI etc to run without adding support for this minor variant. The
"s" device differs from the non "s" device only in
thermal limits and voltage/frequency characteristics.
Microchip:
Redo the mpfs clock setup yet again, to something approaching correct.
The original binding conjured up for the platform was wildly inaccurate,
and even with the original improvements, a bigger change to using
syscons was required to support several peripherals that also inhabit
the memory regions that the clocks lie in. The damage to the dts isn't
that bad in the end, and of course the whole thing has been done in a
backwards compatible manner, with the code changes being merged a cycle
or two ago in the kernel and like a year ago in U-Boot (the only other
user that I am aware of).
Generic:
Additions to extensions.yaml, mainly for things in the "rva23" profile
that appear for the first time on the Spacemit K3 SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: anlogic: dr1v90: Add "b" ISA extension
dt-bindings: riscv: extensions: Drop unnecessary select schema
dt-bindings: riscv: Add Sha and its comprised extensions
dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl
dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm
dt-bindings: riscv: Add B ISA extension description
dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt
riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board
riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
riscv: dts: microchip: convert clock and reset to use syscon
riscv: dts: microchip: fix mailbox description
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner device tree changes for 6.20
Not many changes this cycle.
- The A523 family of SoCs gained support for SPI controllers.
- Some cleanup of old ARM device tree files to fix DT binding validation
errors.
- D1 and A100 SoCs gained support for their LED controller. This was
from a couple years ago. The driver made it in, but the DT patches
were missed.
- D1 and T113 SoCs gained support for the internal thermal sensor.
* tag 'sunxi-dt-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
riscv: dts: allwinner: d1: Add CPU thermal sensor and zone
ARM: dts: allwinner: Replace status "failed" with "fail"
riscv: dts: allwinner: d1: Add RGB LEDs to boards
riscv: dts: allwinner: d1: Add LED controller node
arm64: dts: allwinner: a100: Add LED controller node
ARM: dts: allwinner: sun5i-a13-utoo-p66: delete "power-gpios" property
arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash
arm64: dts: allwinner: sun55i: Add SPI controllers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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into soc/dt
RISC-V SpacemiT DT changes for 6.20
- Disable Ethernet PHY auto sleep mode
- Add pinctrl IO power support
- Add K3 Pico-ITX board
- Add support for K3 SoC
- Add DWC USB support
- Add reset for eMMC(sdhci)/I2C
- Add PCIe support
- Support PMIC for Jupiter board
* tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux:
riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi
riscv: dts: spacemit: pinctrl: update register and IO power
riscv: dts: spacemit: add K3 Pico-ITX board support
riscv: dts: spacemit: add initial support for K3 SoC
dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
dt-bindings: interrupt-controller: add SpacemiT K3 APLIC
dt-bindings: timer: add SpacemiT K3 CLINT
dt-bindings: riscv: add SpacemiT X100 CPU compatible
riscv: dts: spacemit: k1: Add "b" ISA extension
riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3
riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1
riscv: dts: spacemit: Add USB2 PHY node for K1
riscv: dts: spacemit: sdhci: add reset support
riscv: dts: spacemit: add reset property
riscv: dts: spacemit: PCIe and PHY-related updates
riscv: dts: spacemit: Add a PCIe regulator
riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter
riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter
riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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into soc/dt
RISC-V/Sophgo Devicetrees for v6.20
Sophgo:
For CV18xx serials:
Update RX/TX FIFO size to fix the USB transfer issue.
For SG2042:
Optimize the DTS file format, including moving PLIC/CLINT
nodes into cpu dtsi and sorting peripheral nodes by address.
In addition, we also enable RTC for Pioneerbox.
For SG2044:
Add "b" ISA extension to fix dtbs_check warnings.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux:
riscv: dts: sophgo: sg2044: Add "b" ISA extension
riscv: dts: sophgo: fix the node order of SG2042 peripheral
riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V Pioneer
riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The sun20i THS (built in CPU thermal sensor) is supported in code, but
was never added to the device tree. So, add it to the device tree,
along with a thermal zone for the CPU.
Signed-off-by: Alex Studer <alex@studer.dev>
Changes since v1:
- Move include before defines in sun20i-d1s.dtsi
- Fix register size for thermal-sensor@2009400
- Move thermal-sensor@2009400 in SoC to match register address sorting
- Add thermal-zone for sun8i-t113s.dtsi and fix missing cooling-cells
Link: https://lore.kernel.org/r/20250218020629.1476126-1-alex@studer.dev
Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
Link: https://patch.msgid.link/20260113182951.1059690-1-lukas.schmid@netcube.li
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
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On the SpacemiT K1 platform, the MAC can't read statistics when the PHY
clock stops. Disable Link Down Power Saving Mode for the YT8531C PHY on
OrangePi R2S and RV2 boards to avoid reading statistics timeout logs.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260120100001.1285624-2-amadeus@jmu.edu.cn
Signed-off-by: Yixun Lan <dlan@kernel.org>
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Change the size of the reg register to 0x1000 to match the hardware.
This register range covers the IO power domain's register addresses.
The IO power domain registers are protected. In order to access the
protected IO power domain registers, a valid unlock sequence must be
performed by writing the required keys to the AIB Secure Access Register
(ASAR).
The ASAR register resides within the APBC register address space.
A corresponding syscon property `spacemit,apbc` is added to allow
the pinctrl driver to access this register.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
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K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT
K3 SoC.
This minimal device tree enables booting into a serial console with UART
output.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
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SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
Add nodes of uarts, timer and interrupt-controllers. Also add M-mode
APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware
topology and ready for potential firmware usage.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
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"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs
(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency
checking rule is now enforced, which requires that when zba, zbb, and zbs
are all specified, "b" must be added as well. Failing to do this will
cause dtbs_check schema check warnings.
According to uabi.rst, as a single-letter extension, "b" should be added
after "c" in canonical order.
Update k1.dtsi to conform to this rule.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
Banana Pi F3 board.
The board utilizes a VLI VL817 hub, which requires two separate power
supplies: one VBUS and one for hub itself. Add two GPIO-controlled
fixed-regulators to manage this.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC.
The controller resides on the 'storage-bus' and uses its DMA
translations.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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K1's DWC3 USB 3.0 controller requires two separate PHYs to function:
the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed,
Full-Speed, etc.).
Add node for this second USB 2.0 PHY (usbphy2).
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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Request two reset line explicitly for SDHCI controller.
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://lore.kernel.org/r/20251223-07-k1-sdhci-reset-v2-3-5b8248cfc522@gentoo.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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Add resets property to K1 I2C node.
Signed-off-by: Encrow Thorne <jyc0019@gmail.com>
Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
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"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs
(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency
checking rule is now enforced, which requires that when zba, zbb, and zbs
are all specified, "b" must be added as well. Failing to do this will
cause dtbs_check schema check warnings.
According to uabi.rst, as a single-letter extension, "b" should be added
after "c" in canonical order.
Update sg2044-cpus.dtsi to conform to this rule.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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