summaryrefslogtreecommitdiffstats
path: root/arch/riscv/errata/sifive
AgeCommit message (Expand)AuthorLines
2026-01-25errata/sifive: remove unreliable warn_miss_errataAndreas Schwab-18/+0
2024-11-07asm-generic: introduce text-patching.hMike Rapoport (Microsoft)-1/+1
2024-09-15riscv: errata: sifive: Use SYM_*() assembly macrosJisheng Zhang-4/+4
2024-07-22riscv: Extend cpufeature.c to detect vendor extensionsCharlie Jenkins-0/+3
2024-04-29riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland-0/+5
2023-04-29RISC-V: fix sifive and thead section mismatches in errataRandy Dunlap-5/+3
2023-04-28Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds-4/+4
2023-03-14riscv: alternatives: Rename errata_id to patch_idAndrew Jones-3/+3
2023-03-14riscv: alternatives: Remove unnecessary define and unused structAndrew Jones-1/+1
2023-03-07RISC-V: fix taking the text_mutex twice during sifive errata patchingConor Dooley-1/+1
2023-02-21RISC-V: take text_mutex during alternative patchingConor Dooley-0/+3
2023-01-31riscv: switch to relative alternative entriesJisheng Zhang-1/+2
2022-07-07riscv: don't warn for sifive erratas in modulesHeiko Stuebner-1/+2
2022-05-11riscv: add memory-type errata for T-HeadHeiko Stuebner-1/+6
2022-05-11riscv: implement module alternativesHeiko Stuebner-5/+9
2022-05-11riscv: allow different stages with alternativesHeiko Stuebner-1/+2
2021-06-01riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent-1/+1
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen-0/+18
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen-0/+59
2021-04-26riscv: sifive: Add SiFive alternative portsVincent Chen-0/+69