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path: root/arch/riscv/errata
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2022-09-13RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt-0/+1
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt-0/+20
2022-08-06Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds-26/+12
2022-08-03riscv: implement cache-management errata for T-Head SoCsHeiko Stuebner-0/+20
2022-07-07riscv: don't warn for sifive erratas in modulesHeiko Stuebner-1/+2
2022-06-16riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner-26/+12
2022-05-11riscv: add memory-type errata for T-HeadHeiko Stuebner-1/+100
2022-05-11riscv: implement module alternativesHeiko Stuebner-5/+9
2022-05-11riscv: allow different stages with alternativesHeiko Stuebner-1/+2
2022-05-11riscv: integrate alternatives better into the main architectureHeiko Stuebner-76/+0
2022-01-09riscv: errata: alternative: mark vendor_patch_func __initdataJisheng Zhang-1/+2
2021-06-01riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent-1/+1
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen-0/+18
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen-0/+59
2021-04-26riscv: sifive: Add SiFive alternative portsVincent Chen-0/+75
2021-04-26riscv: Introduce alternative mechanism to apply errata solutionVincent Chen-0/+70