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path: root/arch/riscv/kernel/cpu.c
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2022-08-11RISC-V: Add Sstc extension supportPalmer Dabbelt-0/+1
2022-08-11RISC-V: Enable sstc extension parsing from DTAtish Patra-0/+1
2022-08-11arch/riscv: add Zihintpause supportDao Lu-0/+1
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt-0/+1
2022-07-28riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner-0/+1
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L-11/+15
2022-05-21riscv: Don't output a bogus mmu-type on a no MMU kernelNiklas Cassel-0/+4
2022-05-11riscv: add RISC-V Svpbmt extension supportHeiko Stuebner-0/+1
2022-03-31riscv: cpu.c: don't use kernel-doc markers for commentsRandy Dunlap-2/+2
2022-03-30RISC-V: Fix a comment typo in riscv_of_parent_hartid()Atish Patra-1/+1
2022-03-21perf: RISC-V: Add support for SBI PMU and SscofpmfPalmer Dabbelt-0/+1
2022-03-21RISC-V: Add sscofpmf extension supportAtish Patra-0/+1
2022-03-17RISC-V: Provide a fraemework for RISC-V ISA extensionsPalmer Dabbelt-2/+63
2022-03-17RISC-V: Improve /proc/cpuinfo output for ISA extensionsAtish Patra-2/+63
2022-02-14riscv: mm: Set sv57 on defaultlyQinglin Pan-1/+3
2022-01-19riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfoAlexandre Ghiti-11/+12
2021-10-20riscv: Use of_get_cpu_hwid()Rob Herring-1/+2
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel-0/+16
2019-10-28RISC-V: Remove unsupported isa string info printAtish Patra-42/+3
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner-9/+1
2019-04-30RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra-2/+1
2019-03-04RISC-V: Remove NR_CPUs check during hartid search from DTAtish Patra-4/+0
2019-02-11riscv: treat cpu devicetree nodes without status as enabledJohan Hovold-7/+3
2019-02-11riscv: fix riscv_of_processor_hartid() commentJohan Hovold-9/+9
2019-02-11riscv: add missing newlines to printk messagesJohan Hovold-1/+1
2018-12-21RISC-V: Fix of_node_* refcountAtish Patra-0/+1
2018-11-20RISC-V: recognize S/U mode bits in print_isaPatrick Stählin-3/+6
2018-10-22RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel-4/+6
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra-3/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt-2/+5
2018-10-22RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt-7/+61
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt-0/+108