linux - Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/

Age	Commit message (Expand)	Author	Lines
2023-05-05	Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEAD	Paolo Bonzini	-0/+2
2023-04-21	RISC-V: Detect AIA CSRs from ISA string	Anup Patel	-0/+2
2023-04-18	Merge patch series "RISC-V Hardware Probing User Interface"	Palmer Dabbelt	-6/+2
2023-04-18	RISC-V: Move struct riscv_cpuinfo to new header	Evan Green	-6/+2
2023-03-15	Merge patch series "RISC-V: Apply Zicboz to clear_page"	Palmer Dabbelt	-0/+1
2023-03-14	RISC-V: Add Zicboz detection and block size parsing	Andrew Jones	-0/+1
2023-03-09	Merge patch series "riscv, mm: detect svnapot cpu support at runtime"	Palmer Dabbelt	-0/+1
2023-03-07	riscv: mm: modify pte format for Svnapot	Qinglin Pan	-0/+1
2023-02-21	RISC-V: fix ordering of Zbb extension	Heiko Stuebner	-1/+1
2023-01-31	RISC-V: add zbb support to string functions	Heiko Stuebner	-0/+1
2023-01-19	Merge patch series "Putting some basic order on isa extension lists"	Palmer Dabbelt	-15/+38
2023-01-17	RISC-V: resort all extensions in consistent orders	Conor Dooley	-2/+2
2023-01-17	RISC-V: clarify ISA string ordering rules in cpu.c	Conor Dooley	-13/+36
2022-12-14	Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	-3/+27
2022-10-27	RISC-V: Fix /proc/cpuinfo cpumask warning	Andrew Jones	-0/+3
2022-10-27	RISC-V: Cache SBI vendor values	Heiko Stuebner	-3/+27
2022-10-14	Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	-0/+51
2022-10-13	RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output	Palmer Dabbelt	-0/+51
2022-10-11	Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm	Linus Torvalds	-0/+1
2022-10-06	RISC-V: Print SSTC in canonical order	Palmer Dabbelt	-1/+1
2022-10-03	RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output	Anup Patel	-0/+51
2022-10-02	RISC-V: Probe Svinval extension form ISA string	Mayuresh Chitale	-0/+1
2022-08-11	RISC-V: Add Sstc extension support	Palmer Dabbelt	-0/+1
2022-08-11	RISC-V: Enable sstc extension parsing from DT	Atish Patra	-0/+1
2022-08-11	arch/riscv: add Zihintpause support	Dao Lu	-0/+1
2022-08-10	riscv: implement Zicbom-based CMO instructions + the t-head variant	Palmer Dabbelt	-0/+1
2022-07-28	riscv: Add support for non-coherent devices using zicbom extension	Heiko Stuebner	-0/+1
2022-07-19	riscv: cpu: Add 64bit hartid support on RV64	Sunil V L	-11/+15
2022-05-21	riscv: Don't output a bogus mmu-type on a no MMU kernel	Niklas Cassel	-0/+4
2022-05-11	riscv: add RISC-V Svpbmt extension support	Heiko Stuebner	-0/+1
2022-03-31	riscv: cpu.c: don't use kernel-doc markers for comments	Randy Dunlap	-2/+2
2022-03-30	RISC-V: Fix a comment typo in riscv_of_parent_hartid()	Atish Patra	-1/+1
2022-03-21	perf: RISC-V: Add support for SBI PMU and Sscofpmf	Palmer Dabbelt	-0/+1
2022-03-21	RISC-V: Add sscofpmf extension support	Atish Patra	-0/+1
2022-03-17	RISC-V: Provide a fraemework for RISC-V ISA extensions	Palmer Dabbelt	-2/+63
2022-03-17	RISC-V: Improve /proc/cpuinfo output for ISA extensions	Atish Patra	-2/+63
2022-02-14	riscv: mm: Set sv57 on defaultly	Qinglin Pan	-1/+3
2022-01-19	riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo	Alexandre Ghiti	-11/+12
2021-10-20	riscv: Use of_get_cpu_hwid()	Rob Herring	-1/+2
2020-06-09	RISC-V: Rename and move plic_find_hart_id() to arch directory	Anup Patel	-0/+16
2019-10-28	RISC-V: Remove unsupported isa string info print	Atish Patra	-42/+3
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	-9/+1
2019-04-30	RISC-V: Add RISC-V specific arch_match_cpu_phys_id	Atish Patra	-2/+1
2019-03-04	RISC-V: Remove NR_CPUs check during hartid search from DT	Atish Patra	-4/+0
2019-02-11	riscv: treat cpu devicetree nodes without status as enabled	Johan Hovold	-7/+3
2019-02-11	riscv: fix riscv_of_processor_hartid() comment	Johan Hovold	-9/+9
2019-02-11	riscv: add missing newlines to printk messages	Johan Hovold	-1/+1
2018-12-21	RISC-V: Fix of_node_* refcount	Atish Patra	-0/+1
2018-11-20	RISC-V: recognize S/U mode bits in print_isa	Patrick Stählin	-3/+6
2018-10-22	RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo	Anup Patel	-4/+6