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path: root/arch/riscv/kernel/smpboot.c
AgeCommit message (Expand)AuthorLines
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L-4/+5
2022-05-11riscv: move boot alternatives to after fill_hwcapHeiko Stuebner-2/+0
2022-05-11riscv: integrate alternatives better into the main architectureHeiko Stuebner-2/+0
2022-01-20RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra-1/+1
2021-05-12sched/core: Initialize the idle task with preemption disabledValentin Schneider-1/+0
2021-04-26riscv: Introduce alternative mechanism to apply errata solutionVincent Chen-0/+4
2021-01-14riscv: Add numa support for riscv64 platformAtish Patra-1/+11
2020-08-20RISC-V: Remove CLINT related code from timer and archAnup Patel-1/+0
2020-08-20RISC-V: Add mechanism to provide custom IPI operationsAnup Patel-2/+1
2020-08-04RISC-V: Fix build warning for smpboot.cAtish Patra-1/+1
2020-07-30RISC-V: Setup exception vector earlyAtish Patra-1/+1
2020-07-30riscv: Fixup lockdep_assert_held with wrong param cpu_runningZong Li-1/+0
2020-06-29RISC-V: Use a local variable instead of smp_processor_id()Greentime Hu-3/+4
2020-03-31RISC-V: Add supported for ordered booting method using HSMAtish Patra-1/+1
2020-03-31RISC-V: Add cpu_ops and modify default booting methodAtish Patra-21/+30
2019-11-17riscv: provide native clint access for M-modeChristoph Hellwig-0/+4
2019-10-28riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley-1/+1
2019-10-28riscv: add missing header file includesPaul Walmsley-0/+1
2019-10-28riscv: add prototypes for assembly language functions from head.SPaul Walmsley-0/+2
2019-07-22RISC-V: Parse cpu topology during boot.Atish Patra-0/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner-9/+1
2019-05-16RISC-V: Support nr_cpus command line option.Atish Patra-1/+9
2019-04-30RISC-V: Implement nosmp commandline option.Atish Patra-1/+11
2019-03-04RISC-V: Compare cpuid with NR_CPUS before mapping.Atish Patra-0/+5
2019-03-04RISC-V: Do not wait indefinitely in __cpu_upAtish Patra-3/+12
2019-02-11riscv: use for_each_of_cpu_node iteratorJohan Hovold-2/+2
2019-01-23RISC-V: fix bad use of of_node_putAndreas Schwab-5/+1
2018-12-21RISC-V: Fix of_node_* refcountAtish Patra-1/+5
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra-9/+16
2018-10-22RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra-2/+3
2018-10-22RISC-V: Use mmgrab()Palmer Dabbelt-1/+2
2018-10-22RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt-4/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt-1/+1
2018-10-22RISC-V: Disable preemption before enabling interruptsAtish Patra-1/+5
2018-10-22RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt-0/+4
2018-08-13clocksource: new RISC-V SBI timer driverPalmer Dabbelt-1/+0
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt-0/+114