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2025-04-24riscv: uprobes: Add missing fence.i after building the XOL bufferBjörn Töpel-8/+2
2025-04-23Fix mis-uses of 'cc-option' for warning disablementLinus Torvalds-2/+2
2025-04-18Merge patch series "riscv: misaligned: Add ZCB handling and fix sleeping func...Palmer Dabbelt-2/+19
2025-04-18riscv: misaligned: Add handling for ZCB instructionsNylon Chen-0/+17
2025-04-18riscv: misaligned: fix sleeping function called during misaligned access hand...Nylon Chen-2/+2
2025-04-16Merge tag 'riscv-fixes-6.15-rc3' of ssh://gitolite.kernel.org/pub/scm/linux/k...Palmer Dabbelt-22/+64
2025-04-16Merge patch series "riscv: Rework the arch_kgdb_breakpoint() implementation"Palmer Dabbelt-0/+6
2025-04-16riscv: KGDB: Remove ".option norvc/.option rvc" for kgdb_compiled_breakWangYuli-3/+1
2025-04-16riscv: KGDB: Do not inline arch_kgdb_breakpoint()WangYuli-0/+8
2025-04-16RISC-V: vDSO: Wire up getrandom() vDSO implementationXi Ruoyao-0/+267
2025-04-14riscv: module: Allocate PLT entries for R_RISCV_PLT32Samuel Holland-6/+7
2025-04-14riscv: module: Fix out-of-bounds relocation accessSamuel Holland-1/+1
2025-04-14riscv: Properly export reserved regions in /proc/iomemBjörn Töpel-1/+35
2025-04-14riscv: Fix unaligned access info messagesAndrew Jones-14/+21
2025-04-07riscv: Use kvmalloc_array on relocation_hashtableWill Pierce-4/+5
2025-04-04Merge tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds-173/+367
2025-04-01Merge tag 'mm-stable-2025-03-30-16-52' of git://git.kernel.org/pub/scm/linux/...Linus Torvalds-1/+1
2025-04-01riscv/kexec_file: Handle R_RISCV_64 in purgatory relocatorYao Zi-0/+3
2025-04-01Merge patch series "Add some validation for vector, vector crypto and fp stuff"Alexandre Ghiti-40/+103
2025-04-01riscv: print hartid on bringupYunhui Cui-0/+6
2025-03-25Merge tag 'timers-vdso-2025-03-23' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds-97/+11
2025-03-25RISC-V: add f & d extension validation checksConor Dooley-2/+29
2025-03-25RISC-V: add vector crypto extension validation checksConor Dooley-16/+33
2025-03-25RISC-V: add vector extension validation checksConor Dooley-20/+40
2025-03-20Merge patch series "riscv: Add runtime constant support"Alexandre Ghiti-5/+8
2025-03-20riscv: Add runtime constant supportCharlie Jenkins-0/+3
2025-03-20riscv: Move nop definition to insn-def.hCharlie Jenkins-5/+5
2025-03-20Merge patch series "riscv: Unaligned access speed probing fixes and skipping"Alexandre Ghiti-101/+150
2025-03-19riscv: Add parameter for skipping access speed testsAndrew Jones-66/+121
2025-03-19riscv: Fix set up of vector cpu hotplug callbackAndrew Jones-15/+16
2025-03-19riscv: Fix set up of cpu hotplug callbacksAndrew Jones-14/+13
2025-03-19riscv: Change check_unaligned_access_speed_all_cpus to voidAndrew Jones-10/+5
2025-03-19riscv: Fix check_unaligned_access_all_cpusAndrew Jones-10/+7
2025-03-19riscv: Fix riscv_online_cpu_vecAndrew Jones-2/+4
2025-03-19riscv: Annotate unaligned access init functionsAndrew Jones-11/+11
2025-03-19riscv: hwprobe: export Zaamo and Zalrsc extensionsClément Léger-0/+2
2025-03-19riscv: add parsing for Zaamo and Zalrsc extensionsClément Léger-1/+8
2025-03-19riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrac...Pu Lehui-13/+11
2025-03-18riscv: Fix missing __free_pages() in check_vector_unaligned_access()Alexandre Ghiti-1/+4
2025-03-18riscv: Fix the __riscv_copy_vec_words_unaligned implementationTingbo Liao-1/+1
2025-03-18riscv: remove redundant CMDLINE_FORCE checkZixian Zeng-5/+0
2025-03-18Merge patch series "Support SSTC while PM operations"Alexandre Ghiti-0/+14
2025-03-18riscv: Add stimecmp save and restoreNick Hu-0/+14
2025-03-18riscv: Simplify base extension checks and direct boolean returnChin Yik Ming-5/+3
2025-03-18riscv: Remove unused TASK_TI_FLAGSJinjie Ruan-1/+0
2025-03-18RISC-V: hwprobe: Expose Zicbom extension and its block sizeYunhui Cui-1/+7
2025-03-18RISC-V: Enable cbo.clean/flush in usermodeYunhui Cui-0/+8
2025-03-18Merge patch series "riscv: Add bfloat16 instruction support"Alexandre Ghiti-0/+38
2025-03-18riscv: hwprobe: export bfloat16 ISA extensionInochi Amaoto-0/+3
2025-03-18riscv: add ISA extension parsing for bfloat16 ISA extensionInochi Amaoto-0/+35