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path: root/arch/x86/kernel/cpu/cacheinfo.c
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2025-09-17x86/cpu/cacheinfo: Simplify cacheinfo_amd_init_llc_id() using _cpuid4_infoK Prateek Nayak-27/+21
2025-05-16x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameterAhmed S. Darwish-7/+7
2025-05-16x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()Ahmed S. Darwish-2/+2
2025-05-15x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID headerAhmed S. Darwish-1/+1
2025-04-14x86/platform/amd: Move the <asm/amd_nb.h> header to <asm/amd/nb.h>Ingo Molnar-1/+1
2025-04-11x86/cacheinfo: Standardize header files and CPUID referencesAhmed S. Darwish-10/+10
2025-04-09x86/cacheinfo: Properly parse CPUID(0x80000006) L2/L3 associativityAhmed S. Darwish-2/+8
2025-04-09x86/cacheinfo: Properly parse CPUID(0x80000005) L1d/L1i associativityAhmed S. Darwish-3/+6
2025-03-25x86/cacheinfo: Apply maintainer-tip coding style fixesAhmed S. Darwish-108/+107
2025-03-25x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache()Ahmed S. Darwish-18/+14
2025-03-25x86/cacheinfo: Relocate CPUID leaf 0x4 cache_type mappingAhmed S. Darwish-7/+8
2025-03-25x86/cacheinfo: Extract out cache self-snoop checksAhmed S. Darwish-11/+13
2025-03-25x86/cacheinfo: Extract out cache level topology ID calculationAhmed S. Darwish-7/+12
2025-03-25x86/cacheinfo: Separate Intel CPUID leaf 0x4 handlingAhmed S. Darwish-56/+54
2025-03-25x86/cacheinfo: Separate CPUID leaf 0x2 handling and post-processing logicAhmed S. Darwish-48/+58
2025-03-25x86/cacheinfo: Use consolidated CPUID leaf 0x2 descriptor tableAhmed S. Darwish-106/+8
2025-03-25x86/cacheinfo: Use enums for cache descriptor typesAhmed S. Darwish-7/+2
2025-03-25x86/cacheinfo: Clarify type markers for CPUID leaf 0x2 cache descriptorsAhmed S. Darwish-76/+76
2025-03-25x86/cacheinfo: Rename 'struct _cpuid4_info_regs' to 'struct _cpuid4_info'Ahmed S. Darwish-11/+11
2025-03-25x86/cacheinfo: Separate Intel and AMD CPUID leaf 0x4 code pathsAhmed S. Darwish-41/+54
2025-03-25x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate fileAhmed S. Darwish-298/+0
2025-03-25x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regsAhmed S. Darwish-16/+29
2025-03-25x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d callsAhmed S. Darwish-15/+15
2025-03-25x86/cacheinfo: Standardize _cpuid4_info_regs instance namingAhmed S. Darwish-48/+49
2025-03-25x86/cacheinfo: Align ci_info_init() assignment expressionsAhmed S. Darwish-13/+10
2025-03-25x86/cacheinfo: Constify _cpuid4_info_regs instancesAhmed S. Darwish-3/+4
2025-03-25x86/cacheinfo: Use proper name for cacheinfo instancesThomas Gleixner-46/+43
2025-03-25x86/cacheinfo: Properly name amd_cpuid4()'s first parameterThomas Gleixner-9/+6
2025-03-25x86/cacheinfo: Refactor CPUID leaf 0x2 cache descriptor lookupThomas Gleixner-24/+20
2025-03-25x86/cacheinfo: Use CPUID leaf 0x2 parsing helpersAhmed S. Darwish-18/+6
2025-03-25x86/cacheinfo: Remove CPUID leaf 0x2 parsing loopAhmed S. Darwish-40/+37
2025-03-04x86/cacheinfo: Remove unnecessary headers and reorder the restAhmed S. Darwish-7/+5
2025-03-04x86/cacheinfo: Remove the P4 trace leftovers for realThomas Gleixner-16/+3
2025-03-04x86/cacheinfo: Validate CPUID leaf 0x2 EDX outputAhmed S. Darwish-1/+1
2024-12-06x86/cacheinfo: Delete global num_cache_leavesRicardo Neri-22/+21
2024-03-11Merge tag 'x86_mtrr_for_v6.9_rc1' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds-3/+4
2024-02-20x86/pat: Simplify the PAT programming protocolKirill A. Shutemov-3/+4
2024-02-16x86/cpu/topology: Get rid of cpuinfo::x86_max_coresThomas Gleixner-1/+1
2024-02-15x86/cpu: Provide an AMD/HYGON specific topology parserThomas Gleixner-2/+2
2024-02-15x86/cpu/amd: Provide a separate accessor for Node IDThomas Gleixner-1/+1
2023-10-10x86/cpu: Move cpu_l[l2]c_id into topology infoThomas Gleixner-21/+12
2023-10-10x86/cpu: Move cpu_die_id into topology infoThomas Gleixner-1/+1
2023-10-10x86/cpu: Move phys_proc_id into topology infoThomas Gleixner-2/+2
2023-10-10x86/cpu: Encapsulate topology information in cpuinfo_x86Thomas Gleixner-10/+10
2023-05-15x86/cpu/cacheinfo: Remove cpu_callout_mask dependencyThomas Gleixner-4/+17
2023-02-11x86/cacheinfo: Remove unused trace variableBorislav Petkov (AMD)-4/+1
2022-11-10x86/cacheinfo: Switch cache_ap_init() to hotplug callbackJuergen Gross-3/+15
2022-11-10x86: Decouple PAT and MTRR handlingJuergen Gross-1/+2
2022-11-10x86/mtrr: Add a stop_machine() handler calling only cache_cpu_init()Juergen Gross-1/+58
2022-11-10x86/mtrr: Let cache_aps_delayed_init replace mtrr_aps_delayed_initJuergen Gross-0/+12
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