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path: root/drivers/clk/meson/Kconfig
AgeCommit message (Expand)AuthorLines
2025-12-15clk: meson: t7: add t7 clock peripherals controller driverJian Hu-0/+13
2025-12-15clk: meson: t7: add support for the T7 SoC PLL clockJian Hu-0/+15
2025-09-04clk: amlogic: drop meson-clkceeJerome Brunet-8/+5
2025-07-02clk: amlogic: get regmap with clk_regmap_initJerome Brunet-0/+1
2025-06-23clk: amlogic: axg-audio: use the auxiliary reset driverJerome Brunet-1/+2
2025-05-15clk: meson: Do not enable by default during compile testingKrzysztof Kozlowski-8/+8
2024-12-02clk: amlogic: axg-audio: revert reset implementationJerome Brunet-1/+1
2024-11-14clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUXArnd Bergmann-1/+1
2024-10-14clk: amlogic: axg-audio: use the auxiliary reset driverJerome Brunet-0/+1
2024-06-04clk: meson: c3: add c3 clock peripherals controller driverXianwei Zhao-0/+14
2024-06-04clk: meson: c3: add support for the C3 SoC PLL clockXianwei Zhao-0/+13
2024-04-10clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCFNeil Armstrong-0/+1
2024-04-10clk: meson: add vclk driverNeil Armstrong-0/+4
2023-10-23clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILSArnd Bergmann-0/+2
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu-0/+11
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu-0/+12
2023-08-08clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKSNeil Armstrong-0/+1
2023-08-08clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKSNeil Armstrong-0/+1
2023-08-08clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKSNeil Armstrong-0/+2
2023-08-08clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong-0/+1
2023-08-08clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong-0/+1
2023-08-08clk: meson: introduce meson-clkc-utilsNeil Armstrong-0/+3
2023-05-30clk: meson: a1: add Amlogic A1 Peripherals clock controller driverDmitry Rokosov-0/+10
2023-05-30clk: meson: a1: add Amlogic A1 PLL clock controller driverDmitry Rokosov-0/+10
2020-11-23clk: meson: enable building as modulesKevin Hilman-3/+3
2020-11-23clk: meson: Kconfig: fix dependency for G12AKevin Hilman-0/+1
2020-09-10clk: meson: make shipped controller configurableJerome Brunet-9/+17
2019-08-09clk: meson: add g12a cpu dynamic divider driverNeil Armstrong-0/+5
2019-07-29clk: meson: remove clk input helperAlexandre Mergnat-3/+0
2019-07-29clk: meson: remove ee input bypass clocksAlexandre Mergnat-1/+0
2019-07-29clk: meson: remove ao input bypass clocksAlexandre Mergnat-1/+0
2019-07-29clk: meson: axg-audio: migrate to the new parent description methodAlexandre Mergnat-1/+0
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner-0/+1
2019-02-13clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong-0/+2
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet-3/+8
2019-02-04clk: meson: g12a: add peripheral clock controllerJian Hu-0/+12
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet-24/+58
2019-02-02clk: meson: axg-audio does not require sysconJerome Brunet-1/+1
2018-07-09clk: meson: axg: add the audio clock controller driverJerome Brunet-0/+9
2018-07-09clk: meson: add triple phase clock driverJerome Brunet-0/+5
2018-07-09clk: meson: clean-up meson clock configurationJerome Brunet-9/+5
2018-05-15clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai-0/+1
2018-05-15clk: meson: aoclk: refactor common code into dedicated fileYixun Lan-0/+7
2018-03-13clk: meson: use hhi syscon if availableJerome Brunet-0/+2
2018-03-13clk: meson: migrate gates to clk_regmapJerome Brunet-2/+2
2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet-0/+2
2018-03-13clk: meson: switch gxbb ao_clk to clk_regmapJerome Brunet-0/+1
2018-03-13clk: meson: add regmap clocksJerome Brunet-0/+4
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai-0/+8
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl-0/+1