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path: root/drivers/clk/sophgo
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2026-01-22clk: sophgo: sg2042-clkgen: convert from divider_round_rate() to divider_dete...Brian Masney-10/+5
2026-01-22clk: sophgo: cv18xx-ip: convert from divider_round_rate() to divider_determin...Brian Masney-69/+85
2025-09-08clk: sophgo: cv18xx-ip: convert from round_rate() to determine_rate()Brian Masney-4/+6
2025-09-08clk: sophgo: sg2042-pll: remove round_rate() in favor of determine_rate()Brian Masney-17/+9
2025-09-08clk: sophgo: sg2042-clkgen: convert from round_rate() to determine_rate()Brian Masney-8/+9
2025-07-26clk: Fix typosBjorn Helgaas-1/+1
2025-06-19clk: sophgo: Use div64* for 64-by-32 division to simplifyPei Xiao-2/+2
2025-05-07clk: sophgo: Add clock controller support for SG2044 SoCInochi Amaoto-0/+1822
2025-05-07clk: sophgo: Add PLL clock controller support for SG2044 SoCInochi Amaoto-0/+639
2025-05-07clk: sophgo: Add support for newly added precise compatibleInochi Amaoto-0/+2
2024-10-28clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate()Zichen Xie-1/+1
2024-07-18clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug outputDan Carpenter-1/+1
2024-07-16Merge branches 'clk-qcom', 'clk-rockchip', 'clk-sophgo' and 'clk-thead' into ...Stephen Boyd-1/+2061
2024-07-10clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()Nathan Chancellor-10/+7
2024-07-10clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()Li Qiang-1/+1
2024-06-14clk: sophgo: Add SG2042 clock driverChen Wang-0/+2063
2024-06-03clk: sophgo: add missing MODULE_DESCRIPTION() macroJeff Johnson-0/+1
2024-04-19clk: sophgo: avoid open-coded 64-bit divisionArnd Bergmann-2/+1
2024-04-11clk: sophgo: Make synthesizer struct staticInochi Amaoto-6/+6
2024-04-11clk: sophgo: Add clock support for SG2000 SoCInochi Amaoto-0/+15
2024-04-11clk: sophgo: Add clock support for CV1810 SoCInochi Amaoto-0/+196
2024-04-11clk: sophgo: Add clock support for CV1800 SoCInochi Amaoto-0/+3300