summaryrefslogtreecommitdiffstats
path: root/drivers/clk/zte
AgeCommit message (Expand)AuthorLines
2017-06-19clk: zx296718: export I2S mux clocksShawn Guo-4/+4
2017-04-12clk: zte: Mark pll config tables as constStephen Boyd-2/+2
2017-04-12clk: zte: add pll_vga clock for zx296718Shawn Guo-0/+24
2017-04-12clk: zte: pd_bit is not 0 on zx296718Shawn Guo-2/+16
2017-04-12clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksShawn Guo-3/+3
2017-02-10clk: zte: add i2s clocks for zx296718Baoyou Xie-0/+4
2017-01-09clk: zte: add audio clocks for zx296718Jun Nie-0/+275
2017-01-09clk: zx296718: do not panic on failureShawn Guo-9/+18
2016-09-23clk: zx296718: register driver earlier with core_initcallShawn Guo-1/+5
2016-09-16clk: zx: fix pointer case warningsArnd Bergmann-10/+10
2016-09-16clk: zx296718: use builtin_platform_driver to simplify the codeWei Yongjun-5/+1
2016-09-14clk: zx: register ZX296718 clocksJun Nie-0/+1050
2016-09-14clk: zx: reform pll config info to ease code extensionJun Nie-9/+16
2016-04-15clk: zte: Remove CLK_IS_ROOTStephen Boyd-2/+1
2015-07-28clk: zx: Constify parent names in clock init dataJun Nie-20/+20
2015-07-28clk: zx: Add audio and GPIO clock for zx296702Jun Nie-2/+90
2015-07-28clk: zx: Add audio div clock method for zx296702Jun Nie-3/+149
2015-06-11clk: zx: add clock support to zx296702Jun Nie-0/+863