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2021-08-29Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds-1/+1
2021-08-28clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereferenceAdam Ford-1/+1
2021-08-21Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds-19/+37
2021-08-05clk: qcom: gdsc: Ensure regulator init state matches GDSC stateBjorn Andersson-18/+36
2021-08-05clk: imx6q: fix uart earlycon unworkDong Aisheng-1/+1
2021-08-03Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds-7/+25
2021-07-31clk: fix leak on devm_clk_bulk_get_all() unwindBrian Norris-1/+8
2021-07-27clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_opsDmitry Osipenko-0/+10
2021-07-27clk: qcom: smd-rpm: Fix MSM8936 RPM_SMD_PCNOC_A_CLKShawn Guo-1/+1
2021-07-26clk: hisilicon: hi3559a: select RESET_HISIRandy Dunlap-0/+1
2021-07-26clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi-5/+5
2021-07-12dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das-64/+93
2021-07-12clk: renesas: r9a07g044: Add P2 Clock supportBiju Das-0/+5
2021-07-12clk: renesas: r9a07g044: Fix P1 ClockBiju Das-3/+3
2021-07-12clk: renesas: r9a07g044: Rename divider tableBiju Das-3/+4
2021-07-12clk: renesas: rzg2l: Add multi clock PM supportBiju Das-22/+29
2021-07-08Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds-54/+101
2021-07-02Merge branch 'akpm' (patches from Andrew)Linus Torvalds-0/+4
2021-07-01Revert "clk: divider: Switch from .round_rate to .determine_rate by default"Stephen Boyd-9/+9
2021-07-01Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds-1191/+16314
2021-07-01kernel.h: split out panic and oops helpersAndy Shevchenko-0/+4
2021-06-30clk: hisilicon: hi3559a: Drop __init markings everywhereStephen Boyd-20/+19
2021-06-30clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl-10/+9
2021-06-30clk: divider: Switch from .round_rate to .determine_rate by defaultMartin Blumenstingl-9/+9
2021-06-30clk: divider: Add re-usable determine_rate implementationsMartin Blumenstingl-14/+61
2021-06-30clk: k210: Fix k210_clk_set_parent()Damien Le Moal-0/+1
2021-06-30clk: lmk04832: Fix spelling mistakes in dev_err messages and commentsColin Ian King-4/+4
2021-06-30clk: lmk04832: fix return value check in lmk04832_probe()Wang Hai-6/+6
2021-06-30clk: stm32mp1: fix missing spin_lock_init()Wang Hai-0/+1
2021-06-29Merge branches 'clk-st', 'clk-si' and 'clk-hisilicon' into clk-nextStephen Boyd-73/+1710
2021-06-29Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-...Stephen Boyd-186/+2625
2021-06-29Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk...Stephen Boyd-113/+449
2021-06-29Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'cl...Stephen Boyd-296/+931
2021-06-29Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and '...Stephen Boyd-92/+1414
2021-06-28clk: zynqmp: Handle divider specific read only flagRajan Vaja-1/+9
2021-06-28clk: zynqmp: Use firmware specific mux clock flagsRajan Vaja-1/+30
2021-06-28clk: zynqmp: Use firmware specific divider clock flagsRajan Vaja-1/+33
2021-06-28clk: zynqmp: Use firmware specific common clock flagsRajan Vaja-6/+52
2021-06-28clk: lmk04832: Use of match tableStephen Boyd-2/+4
2021-06-28clk: lmk04832: Depend on SPIStephen Boyd-0/+1
2021-06-28clk: stm32mp1: new compatible for secure RCC supportGabriel Fernandez-1/+110
2021-06-27clk: hisilicon: Add clock driver for hi3559A SoCDongjiu Geng-2/+856
2021-06-27clk: si5341: Add sysfs properties to allow checking/resetting device faultsRobert Hancock-0/+96
2021-06-27clk: si5341: Add silabs,iovdd-33 propertyRobert Hancock-1/+9
2021-06-27clk: si5341: Add silabs,xaxb-ext-clk propertyRobert Hancock-2/+7
2021-06-27clk: si5341: Allow different output VDD_SEL valuesRobert Hancock-26/+110
2021-06-27clk: si5341: Update initialization magicRobert Hancock-1/+3
2021-06-27clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock-0/+26
2021-06-27clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock-2/+13
2021-06-27clk: si5341: Wait for DEVICE_READY on startupRobert Hancock-0/+32