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2025-09-21clk: mediatek: Add MT8196 apmixedsys clock supportLaura Nao3-0/+213
2025-09-21clk: mediatek: clk-mtk: Add MUX_DIV_GATE macroLaura Nao1-0/+19
2025-09-21clk: mediatek: clk-gate: Add ops for gates with HW voterLaura Nao2-3/+71
2025-09-21clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate structLaura Nao1-33/+19
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENCLaura Nao3-1/+114
2025-09-21clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()Laura Nao2-0/+17
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENCLaura Nao2-0/+94
2025-09-21clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENCLaura Nao2-1/+44
2025-09-21clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable controlLaura Nao2-0/+8
2025-09-21clk: mediatek: clk-mux: Do not pass flags to clk_mux_determine_rate_flags()Chen-Yu Tsai1-3/+1
2025-09-21clk: mediatek: mt7622-aud: Add missing AFE_MRGIF clockAngeloGioacchino Del Regno1-0/+1
2025-09-21clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26mAngeloGioacchino Del Regno1-1/+1
2025-09-21clk: bcm: rpi: Maximize V3D clockMaíra Canal1-1/+5
2025-09-21clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparingMaíra Canal1-1/+55
2025-09-21clk: bcm: rpi: Add missing logs if firmware failsStefan Wahren1-2/+8
2025-09-19clk: spacemit: fix i2s clockTroy Mitchell1-2/+26
2025-09-19clk: spacemit: introduce pre-div for ddn clockTroy Mitchell3-10/+12
2025-09-19clk: scmi: Add duty cycle ops only when duty cycle is supportedJacky Bai1-2/+9
2025-09-19clk: keystone: sci-clk: use devm_kmemdup_array()Raag Jadav1-4/+1
2025-09-19clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabledMatthias Schiffer1-0/+2
2025-09-19clk: amlogic: fix recent code refactoringMarek Szyprowski1-1/+1
2025-09-19Merge tag 'sunxi-clk-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd1-1/+1
2025-09-17ARM: at91: remove default values for PMC_PLL_ACRCristian Birsan1-5/+2
2025-09-17clk: at91: add ACR in all PLL settingsCristian Birsan5-0/+14
2025-09-17clk: at91: sam9x7: Add peripheral clock id for pmeccBalamanikandan Gunasundar1-0/+1
2025-09-17clk: at91: clk-master: Add check for divide by 3Ryan Wanner1-0/+3
2025-09-17clk: at91: clk-sam9x60-pll: force write to PLL_UPDT registerNicolas Ferre1-36/+39
2025-09-14clk: tegra: dfll: Add CVB tables for Tegra114Svyatoslav Ryhel2-28/+132
2025-09-13clk: sunxi-ng: add support for the A523/T527 MCU CCUChen-Yu Tsai3-0/+476
2025-09-13clk: sunxi-ng: div: support power-of-two dividersChen-Yu Tsai1-0/+18
2025-09-13clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clockChen-Yu Tsai2-17/+18
2025-09-12clk: imx95-blk-ctl: Save/restore registers when RPM routines are calledLaurentiu Palcu1-12/+21
2025-09-12clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structureLaurentiu Palcu1-23/+13
2025-09-12clk: renesas: r9a09g05[67]: Reduce differencesGeert Uytterhoeven2-6/+5
2025-09-12clk: renesas: r9a09g047: Add USB3.0 clocks/resetsBiju Das1-1/+8
2025-09-12clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()Yuan CHen1-2/+5
2025-09-11clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC commentJohan Hovold1-4/+0
2025-09-11clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclkAbel Vesa1-0/+4
2025-09-12clk: sunxi-ng: sun6i-rtc: Add A523 specificsChen-Yu Tsai1-0/+11
2025-09-11clk: renesas: r9a09g056: Add clock and reset entries for I3CLad Prabhakar1-0/+8
2025-09-11clk: renesas: r9a09g057: Add clock and reset entries for I3CLad Prabhakar1-0/+8
2025-09-11clk: tegra: Add DFLL DVCO reset control for Tegra114Svyatoslav Ryhel2-6/+26
2025-09-11dt-bindings: clock: tegra30: Add IDs for CSI pad clocksSvyatoslav Ryhel1-0/+1
2025-09-10clk: sunxi-ng: mp: Fix dual-divider clock rate readbackChen-Yu Tsai1-1/+1
2025-09-09clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc'Imran Shaik1-1/+1
2025-09-08clk: scmi: migrate round_rate() to determine_rate()Brian Masney1-19/+16
2025-09-08clk: ti: fapll: convert from round_rate() to determine_rate()Brian Masney1-21/+27
2025-09-08clk: ti: dra7-atl: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: ti: divider: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: ti: composite: convert from round_rate() to determine_rate()Brian Masney1-3/+3