| Age | Commit message (Expand) | Author | Lines |
|---|---|---|---|
| 2020-01-04 | clocksource: riscv: add notrace to riscv_sched_clock | Zong Li | -1/+1 |
| 2019-11-13 | riscv: add support for MMIO access to the timer registers | Christoph Hellwig | -4/+19 |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig | -4/+4 |
| 2019-09-05 | riscv: don't use the rdtime(h) pseudo-instructions | Christoph Hellwig | -13/+4 |
| 2019-08-06 | RISC-V: Remove per cpu clocksource | Atish Patra | -4/+2 |
| 2019-03-23 | clocksource/drivers/riscv: Fix clocksource mask | Atish Patra | -3/+2 |
| 2019-02-23 | clocksource/drivers/riscv: Add required checks during clock source init | Atish Patra | -3/+20 |
| 2018-12-18 | clocksource/drivers/riscv: Change name riscv_timer to timer-riscv | Daniel Lezcano | -0/+118 |
