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path: root/drivers/cxl
AgeCommit message (Expand)AuthorLines
2023-11-02cxl/pci: Change CXL AER support check to use native AERTerry Bowman-2/+2
2023-10-31cxl/hdm: Remove broken error pathDan Williams-17/+10
2023-10-31cxl/hdm: Fix && vs || bugDan Carpenter-1/+1
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams-6/+40
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams-5/+11
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams-12/+60
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams-129/+406
2023-10-27cxl: Add support for reading CXL switch CDAT tableDave Jiang-5/+20
2023-10-27cxl: Add checksum verification to CDAT from CXLDave Jiang-7/+23
2023-10-27cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang-0/+17
2023-10-27cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang-0/+25
2023-10-27cxl: Add cxl_decoders_committed() helperDave Jiang-6/+15
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter-6/+4
2023-10-27cxl/core/regs: Rename phys_addr in cxl_map_component_regs()Robert Richter-3/+3
2023-10-27cxl/pci: Disable root port interrupts in RCH modeTerry Bowman-0/+32
2023-10-27cxl/pci: Add RCH downstream port error loggingTerry Bowman-0/+96
2023-10-27cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman-0/+46
2023-10-27cxl/pci: Update CXL error logging to use RAS register addressTerry Bowman-13/+31
2023-10-27PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman-0/+1
2023-10-27cxl/pci: Add RCH downstream port AER register discoveryRobert Richter-0/+61
2023-10-27cxl/port: Remove Component Register base address from struct cxl_portRobert Richter-5/+1
2023-10-27cxl/pci: Remove Component Register base address from struct cxl_dev_stateRobert Richter-5/+0
2023-10-27cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter-39/+43
2023-10-27cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_s...Robert Richter-4/+9
2023-10-27cxl/port: Pre-initialize component register mappingsRobert Richter-5/+7
2023-10-27cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter-7/+7
2023-10-27cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams-12/+31
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter-20/+20
2023-10-27cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams-15/+19
2023-10-27cxl/region: Fix x1 root-decoder granularity calculationsJim Harris-1/+8
2023-10-27cxl/region: Fix cxl_region_rwsem lock held when returning to user spaceLi Zhijian-1/+1
2023-10-27cxl/region: Use cxl_calc_interleave_pos() for auto-discoveryAlison Schofield-112/+15
2023-10-27cxl/region: Calculate a target position in a region interleaveAlison Schofield-0/+127
2023-10-26cxl/region: Prepare the decoder match range helper for reuseAlison Schofield-6/+11
2023-10-24cxl/mbox: Remove useless cast in cxl_mem_create_range_info()Alison Schofield-2/+1
2023-10-24cxl/region: Do not try to cleanup after cxl_region_setup_targets() failsJim Harris-7/+7
2023-10-09cxl/mem: Fix shutdown orderDan Williams-1/+1
2023-10-06cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams-49/+90
2023-10-06cxl/pci: Fix sanitize notifier setupDan Williams-42/+50
2023-10-06cxl/pci: Clarify devm host for memdev relative setupDan Williams-12/+13
2023-10-06cxl/pci: Remove inconsistent usage of dev_err_probe()Dan Williams-11/+2
2023-10-06cxl/pci: Remove hardirq handler for cxl_request_irq()Dan Williams-6/+6
2023-09-29cxl/pci: Cleanup 'sanitize' to always pollDan Williams-39/+26
2023-09-29cxl/pci: Remove unnecessary device reference management in sanitize workDan Williams-5/+0
2023-09-22cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook-2/+2
2023-09-22cxl/port: Fix cxl_test register enumeration regressionDan Williams-4/+9
2023-09-15cxl/pci: Update commentIra Weiny-1/+4
2023-09-15cxl/port: Quiet warning messages from the cxl_test environmentDan Williams-2/+7
2023-09-14cxl/region: Refactor granularity select in cxl_port_setup_targets()Alison Schofield-9/+8
2023-09-14cxl/region: Match auto-discovered region decoders by HPA rangeAlison Schofield-1/+23
generated by cgit v1.2.3 (git 2.46.0) at 2026-07-19 21:29:56 +0000