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path: root/drivers/gpu/drm/amd/amdgpu (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-04-08drm/amdgpu/sdma7: update mqd init for UQAlex Deucher1-0/+3
2025-04-08drm/amdgpu/sdma6: update mqd init for UQAlex Deucher1-0/+3
2025-04-08drm/amdgpu/gfx12: update mqd init for UQAlex Deucher1-0/+6
2025-04-08drm/amdgpu: fix IGT CI regression with eviction fenceAmaranath Somalapuram1-0/+3
2025-04-08drm/amdgpu/gfx11: update mqd init for UQAlex Deucher1-0/+8
2025-04-08drm/amdgpu: add some additional members to amdgpu_mqd_propAlex Deucher1-0/+3
2025-04-08drm/amdgpu: handle eviction fence raceShashank Sharma4-6/+17
2025-04-08drm/amdgpu: resume gfx userqueuesShashank Sharma2-5/+179
2025-04-08drm/amdgpu: suspend gfx userqueuesShashank Sharma4-11/+267
2025-04-08drm/amdgpu: add userqueue suspend/resume functionsShashank Sharma1-0/+33
2025-04-08drm/amdgpu: add gfx eviction fence helpersShashank Sharma6-2/+219
2025-04-08drm/amdgpu: add the argument description for gpu_addrSunil Khatri1-0/+1
2025-04-08drm/amdgpu: add new AMDGPU_INFO subquery for userq objectsShashank Sharma1-0/+36
2025-04-08drm/amdgpu: add get_gfx_shadow_info callback for gfx12Shashank Sharma1-0/+29
2025-04-08drm/amdgpu: Modify userq signal/wait struct field namesArunpravin Paneer Selvam1-10/+10
2025-04-08drm/amdgpu: bypass SRIOV check for shadow size infoShashank Sharma2-8/+16
2025-04-08drm/amdgpu: fix userqueue UAPI commentsShashank Sharma2-8/+2
2025-04-08Revert "drm/amdgpu: don't allow userspace to create a doorbell BO"Shashank Sharma1-4/+0
2025-04-08drm/amdgpu: Add input fence to sync bo map/unmapArvind Yadav1-0/+46
2025-04-08drm/amdgpu: add userq specific kernel config for fence ioctlsArunpravin Paneer Selvam1-0/+16
2025-04-08drm/amdgpu: Add gpu_addr support to seq64 allocationArunpravin Paneer Selvam4-7/+15
2025-04-08drm/amdgpu: Add separate array of read and write for BO handlesArunpravin Paneer Selvam1-65/+181
2025-04-08drm/amdgpu: add vm root BO lock before accessing the vmArunpravin Paneer Selvam1-9/+15
2025-04-08drm/amdgpu: Add the missing error handling for xa_store() callArunpravin Paneer Selvam1-2/+4
2025-04-08drm/amdgpu: Few optimization and fixes for userq fence driverArunpravin Paneer Selvam3-21/+31
2025-04-08drm/amdgpu: Remove the MES self testArunpravin Paneer Selvam5-199/+2
2025-04-08drm/amdgpu: update userqueue BOs and PDsArvind Yadav1-9/+104
2025-04-08drm/amdgpu: Enable userq fence interrupt supportArunpravin Paneer Selvam3-13/+20
2025-04-08drm/amdgpu: Add wait IOCTL timeline syncobj supportArunpravin Paneer Selvam1-7/+84
2025-04-08drm/amdgpu: Implement userqueue signal/wait IOCTLArunpravin Paneer Selvam5-8/+482
2025-04-08drm/amdgpu: screen freeze and userq driver crashArunpravin Paneer Selvam1-3/+4
2025-04-08drm/amdgpu: Add mqd support for the fence addressArunpravin Paneer Selvam1-0/+11
2025-04-08drm/amdgpu: Implement a new userqueue fence driverArunpravin Paneer Selvam5-1/+341
2025-04-08drm/amdgpu: add kernel config for gfx-userqueueShashank Sharma5-2/+26
2025-04-08drm/amdgpu: fix MES GFX maskArvind Yadav4-9/+26
2025-04-08drm/amdgpu: enable compute/gfx usermode queueShashank Sharma3-1/+28
2025-04-08drm/amdgpu: enable SDMA usermode queuesArvind Yadav3-1/+22
2025-04-08drm/amdgpu: enable GFX-V11 userqueue supportShashank Sharma3-0/+37
2025-04-08drm/amdgpu: cleanup leftover queuesShashank Sharma1-7/+20
2025-04-08drm/amdgpu: generate doorbell index for userqueueShashank Sharma2-0/+60
2025-04-08drm/amdgpu: map wptr BO into GARTShashank Sharma1-0/+76
2025-04-08drm/amdgpu: map usermode queue into MESShashank Sharma1-0/+74
2025-04-08drm/amdgpu: create context space for usermode queueShashank Sharma1-0/+33
2025-04-08drm/amdgpu: create MES-V11 usermode queue for GFXShashank Sharma3-1/+130
2025-04-08drm/amdgpu: add helpers to create userqueue objectShashank Sharma1-0/+62
2025-04-08drm/amdgpu: add new IOCTL for usermode queueShashank Sharma2-0/+121
2025-04-08drm/amdgpu: add usermode queue base codeShashank Sharma5-0/+52
2025-04-08drm/amdgpu: still cleanup sid.hAlexandre Demers2-29/+13
2025-04-08drm/amdgpu: fill in gmc_v6_0_set_clockgating_state()Alexandre Demers1-16/+28
2025-04-08drm/amdgpu: Reset RAS table if header is invalidLijo Lazar1-5/+7
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-25 13:01:35 +0000