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path: root/drivers/gpu/drm/amd/display/dc/dsc/dcn20
AgeCommit message (Expand)AuthorLines
2026-04-17drm/amd/display: Rework YCbCr422 DSC policyRelja Vojvodic-1/+1
2026-03-30Revert "drm/amd/display: Rework YCbCr422 DSC policy"Relja Vojvodic-1/+1
2026-03-23drm/amd/display: Rework YCbCr422 DSC policyRelja Vojvodic-1/+1
2025-10-28drm/amd/display: Add more DC HW state info to underflow loggingKaren Chen-0/+9
2025-10-13drm/amd/display: Correct slice width calculation for YCbCr420Relja Vojvodic-1/+1
2025-09-15drm/amd/display: Add DSC padding for OVT SupportRelja Vojvodic-1/+2
2025-05-05drm/amd/display: Refactoring DSC enum dsc_bits_per_comp.Bhuvanachandra Pinninti-7/+6
2024-06-27drm/amd/display: Adjust reg field for DSC wait for disconnectRyan Seto-1/+3
2024-06-27drm/amd/display: Reset DSC memory statusDuncan Ma-17/+16
2024-05-08drm/amd/display: reset DSC clock in post unlock updateWenjing Liu-8/+13
2024-04-26drm/amd/display: Add some DCN401 reg name to macro definitionsAurabindo Pillai-0/+11
2023-11-29drm/amd/display: Refactor DSC into component folderBhuvana Chandra Pinninti-0/+1369
generated by cgit v1.2.3 (git 2.46.0) at 2026-07-13 16:25:48 +0000