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path: root/drivers/gpu/drm/amd/include
AgeCommit message (Expand)AuthorLines
2020-08-06drm/amd/display: Read VBIOS Golden Settings TblIgor Kravchenko-1/+53
2020-07-02drm/amdgpu/atomfirmware: update to latest integratedinfotableAlex Deucher-0/+78
2020-07-01drm amdgpu: SI UVD registersSonny Jiang-0/+902
2020-07-01drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)Tom St Denis-4/+4
2020-07-01drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registersTom St Denis-13/+26
2020-07-01drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bitsTom St Denis-5/+109
2020-07-01drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)Tom St Denis-0/+59
2020-07-01drm/amd/powerplay: and smc dpm info struct for sienna_cichlidLikun Gao-0/+123
2020-07-01drm/amdgpu: add firmware_info v3_4 structure for Sienna_CichlidHawking Zhang-0/+36
2020-07-01drm/amdgpu: add vram_info v2_5 in atomfirmware headerHawking Zhang-0/+124
2020-06-03drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlidLikun Gao-0/+1
2020-06-03drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)Likun Gao-0/+90
2020-06-03drm/amdgpu: initialize IP offset for sienna_cichlid (v2)Likun Gao-0/+1168
2020-06-03drm/amd/display: Add dcn30 Headers (v2)Jerry (Fangzhi) Zuo-0/+92947
2020-06-03drm/amdgpu: add VCN3.0 register headers (v2)Leo Liu-0/+7038
2020-06-03drm/amdgpu: Add ATHUB 2.1 header files (v2)Yong Zhao-0/+2901
2020-06-03drm/amdgpu: add GC 10.3 header files (v2)Likun Gao-0/+68433
2020-05-22drm/amdgpu: add apu flags (v2)Alex Deucher-0/+7
2020-05-21drm/amd/display: Add DC Debug mask to disable features for bringupHarry Wentland-0/+7
2020-05-11drm/amd/amdgpu: Add missing GRBM bits for GFX 10.1Tom St Denis-0/+4
2020-05-05drm/amd/display: move location of dmub_srv.h fileAnthony Koo-5/+7
2020-04-22drm/amd/powerplay: revise the way to retrieve the board parametersEvan Quan-0/+102
2020-04-09drm/amdgpu: retire indirect mmio reg support from cgsHawking Zhang-1/+0
2020-04-01drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)Tom St Denis-0/+8
2020-04-01drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own headerTom St Denis-7/+57
2020-04-01drm/amd/amdgpu: Add missing SMUIO v12 register to headersTom St Denis-0/+55
2020-04-01drm/amdgpu: cleanup all virtualization detection routineMonk Liu-0/+6
2020-04-01drm/amd/amdgpu: Add GFX9.1 PWR_MISC_CNTL_STATUS register to headersTom St Denis-0/+7
2020-03-10drm/amdkfd: Consolidate duplicated bo alloc flagsYong Zhao-21/+0
2020-03-06drm/amdgpu: add wafl2 ip headersHawking Zhang-0/+98
2020-03-06drm/amdgpu: add xgmi ip headersHawking Zhang-0/+98
2020-02-28drm/amdkfd: Make get_tile_config() genericYong Zhao-4/+0
2020-02-26drm/amdkfd: Avoid ambiguity by indicating it's cp queueYong Zhao-1/+1
2020-02-26drm/amd: Extend ROCt to surface UUID for devices that have themDivya Shikre-0/+4
2020-02-25amdgpu/gmc_v9: save/restore sdpif regs during S3Shirish S-0/+2
2020-01-30drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for ArcturusJoseph Greathouse-2/+4
2020-01-22drm/amdgpu: add EDC counter registers of gc for ArcturusDennis Li-0/+1012
2020-01-22drm/amdgpu: update mmhub 9.4.1 header files for AcrturusDennis Li-0/+128
2020-01-22drm/amdgpu: added support to get mGPU DRAM baseJohn Clements-0/+11
2020-01-16drm/amd/include: Add OCSC registersRodrigo Siqueira-2/+24
2020-01-16drm/amdkfd: use kiq to load the mqd of hiq queue for gfx v9 (v6)Aaron Liu-0/+4
2020-01-16drm/amdgpu: flush TLB functions removal from kfd2kgd interfaceAlex Sierra-2/+0
2020-01-14drm/amdgpu: add defines for DF and TCP HashingJoseph Greathouse-0/+17
2020-01-14drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file (v2)Tom St Denis-0/+91
2020-01-14drm/amdgpu: add MCUMC_ADDRT0 offset to ip header fileGuchun Chen-0/+4
2019-12-23drm/amdgpu: update the method to get fb_loc of memory training(V4)Tianci.Yin-14/+0
2019-12-23drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support ArcturusJames Zhu-0/+8
2019-12-23drm/amdgpu: add perfmons accessible during df c-statesJonathan Kim-0/+16
2019-12-18drm/amdgpu: move umc offset to one new header file for ArcturusGuchun Chen-0/+31
2019-12-18drm/amdgpu: add dpcs20 registersRoman Li-0/+4559
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