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path: root/drivers/gpu/drm/amd
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2025-11-18drm/amd/display: Cleanup early return in construct_phyTimur Kristóf-6/+7
2025-11-18drm/amd/display: Cleanup uses of the analog flagTimur Kristóf-5/+12
2025-11-18drm/amd/display: Fix warning for analog stream encodersTimur Kristóf-1/+1
2025-11-18drm/amd/display: dc_hw_sequencer.c: remove kernel-doc commentsRandy Dunlap-40/+40
2025-11-18drm/amdgpu: Unregister mce notifierLijo Lazar-1/+27
2025-11-18drm/amd/display: Promote DC to 3.2.359Taimur Hassan-1/+1
2025-11-18drm/amd/display: Ignore Coverity false positiveTaimur Hassan-0/+1
2025-11-18drm/amd/display: Fix pbn to kbps ConversionFangzhi Zuo-36/+23
2025-11-18drm/amd/display: Check DCCG_AUDIO_DTO2 register mask existCharlene Liu-2/+4
2025-11-18drm/amd/display: Add null pointer check in link_dpmsCharlene Liu-1/+5
2025-11-18drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5Ivan Lipski-0/+8
2025-11-18drm/amd/display: Add pipe topology history to dcNicholas Carbones-6/+97
2025-11-18drm/amd/display: Add an HPD filter for HDMIIvan Lipski-0/+144
2025-11-18drm/amd/display: Increase DPCD read retriesMario Limonciello (AMD)-1/+1
2025-11-18drm/amd/display: Move sleep into each retry for retrieve_link_cap()Mario Limonciello (AMD)-4/+5
2025-11-18drm/amd/display: Re-check seamless boot can be enabled or notPaul Hsieh-0/+8
2025-11-18drm/amd/display: Get panel replay capability from DPCDJack Chang-0/+16
2025-11-18drm/amd/display: Add panel replay enablement option and logicJack Chang-2/+168
2025-11-18drm/amd/display: Add panel replay capability detectionJack Chang-0/+25
2025-11-18drm/amd/display: Add interface to capture expected HW state from SW stateGeorge Shen-0/+1048
2025-11-14drm/amdgpu: Use pci_rebar_get_max_size()Ilpo Järvinen-3/+5
2025-11-14drm/amdgpu: Remove driver side BAR release before resizeIlpo Järvinen-7/+1
2025-11-14PCI: Fix restoring BARs on BAR resize rollback pathIlpo Järvinen-1/+3
2025-11-14drm/amdgpu: Use amdgpu by default on SI dedicated GPUs (v2)Timur Kristóf-6/+9
2025-11-14drm/amdgpu: Use amdgpu by default on CIK dedicated GPUsTimur Kristóf-3/+9
2025-11-14drm/amdgpu: Fix the issue of missing ras message on sriov hostYiPeng Chai-15/+10
2025-11-14drm/amdgpu: Add lock to serialize sriov command executionYiPeng Chai-5/+15
2025-11-14drm/amdgpu: Synchronize sriov host to add block_mmsch bit fieldYiPeng Chai-1/+2
2025-11-14drm/amdgpu: use GFP_ATOMIC instead of NOWAIT in the critical pathChristian König-3/+3
2025-11-14drm/amdgpu: avoid memory allocation in the critical code path v3Christian König-49/+14
2025-11-14drm/amdgpu: Enable xgmi extended peer links for sriov guestWill Aitken-2/+2
2025-11-14drm/amdgpu: Update headers for sriov xgmi ext peer link support feature flagWill Aitken-1/+6
2025-11-14drm/amdgpu: Refactor sriov xgmi topology filling to common codeWill Aitken-32/+14
2025-11-14drm/amdgpu: Use amdgpu by default on CIK dedicated GPUsTimur Kristóf-1/+5
2025-11-14drm/amdgpu: Refactor how SI and CIK support is determinedTimur Kristóf-67/+88
2025-11-14drm/amdgpu: Avoid xgmi register accessLijo Lazar-0/+6
2025-11-11drm/amdkfd: Fix GPU mappings for APU after prefetchHarish Kasiviswanathan-0/+2
2025-11-11drm/amdkfd: relax checks for over allocation of save areaJonathan Kim-6/+6
2025-11-11drm/amdgpu/jpeg: Add parse_cs for JPEG5_0_1Sathishkumar S-0/+1
2025-11-11drm/amd/amdgpu: Ensure isp_kernel_buffer_alloc() creates a new BOSultan Alsawaf-0/+2
2025-11-11drm/amd/display: Allow VRR params change if unsynced with the streamIvan Lipski-0/+11
2025-11-11drm/amdgpu: fix lock warning in amdgpu_userq_fence_driver_processJesse.Zhang-2/+3
2025-11-11drm/amdgpu: jump to the correct label on failurePierre-Eric Pelloux-Prayer-1/+1
2025-11-11drm/amdgpu: disable peer-to-peer access for DCC-enabled GC12 VRAM surfacesVitaly Prosyak-0/+12
2025-11-11drm/amdkfd: Fix GPU mappings for APU after prefetchHarish Kasiviswanathan-0/+2
2025-11-11drm/amdgpu/vce1: Workaround PLL timeout on FirePro W9000Timur Kristóf-0/+8
2025-11-11drm/amdgpu/vce1: Enable VCE1 on Tahiti, Pitcairn, Cape Verde GPUsTimur Kristóf-11/+3
2025-11-11drm/amd/pm/si: Hook up VCE1 to SI DPMTimur Kristóf-5/+13
2025-11-11drm/amdgpu/vce1: Ensure VCPU BO is in lower 32-bit address space (v3)Timur Kristóf-0/+75
2025-11-11drm/amdgpu: Check if AID is active before accessLijo Lazar-0/+4