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path: root/drivers/gpu/drm/i915/display/intel_color.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-05-26drm/i915/color: Do not pre-load LUTs with DB registersChaitanya Kumar Borah1-0/+4
2025-05-26drm/i915/display: use GOSUB to program double buffered LUT registersChaitanya Kumar Borah1-9/+30
2025-05-26drm/i915: s/dsb_color_vblank/dsb_colorChaitanya Kumar Borah1-19/+19
2025-04-01drm/i915: reduce intel_wakeref.h dependenciesJani Nikula1-0/+2
2025-03-21drm/i915/color: prefer display->platform.<platform> checksJani Nikula1-10/+6
2025-02-12drm/i915/vrr: Check that the push send bit is clear after delayed vblankVille Syrjälä1-0/+1
2025-02-12drm/i915/vrr: Reorder the DSB "wait for safe window" vs. TRANS_PUSHVille Syrjälä1-0/+2
2025-02-12drm/i915/dsb: Compute use_dsb earlierVille Syrjälä1-2/+4
2025-01-23drm/i915/display: fix typos in i915/display filesNitin Gote1-1/+1
2024-12-16drm/i915/uncore: add to_intel_uncore() and use itJani Nikula1-0/+1
2024-11-28drm/i915/color: Stop using non-posted DSB writes for legacy LUTVille Syrjälä1-10/+20
2024-11-28drm/i915/dsb: Don't use indexed register writes needlesslyVille Syrjälä1-20/+31
2024-10-29drm/i915/color: Make color .get_config() mandatoryVille Syrjälä1-2/+1
2024-10-29drm/i915/color: Convert color management code to intel_displayVille Syrjälä1-317/+319
2024-10-29drm/i915/color: Pimp debugsVille Syrjälä1-17/+31
2024-10-04drm/i915/dsb: Use DSB for plane/color management updatesVille Syrjälä1-22/+3
2024-10-04drm/i915: Plumb 'dsb' all way to the color commit hooksVille Syrjälä1-82/+106
2024-10-04drm/i915: Plumb 'dsb' all way to the plane hooksVille Syrjälä1-1/+1
2024-09-19drm/i915/color: Extract intel_color_modeset()Ville Syrjälä1-0/+17
2024-08-29drm/i915/dsb: Use chained DSBs for LUT programmingVille Syrjälä1-7/+25
2024-08-29drm/i915/dsb: s/dsb/dsb_color_vblank/Ville Syrjälä1-18/+18
2024-06-20drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare()Ville Syrjälä1-1/+1
2024-06-20drm/i915: Pass the whole atomic state to intel_color_prepare_commit()Ville Syrjälä1-3/+8
2024-06-05drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()Ville Syrjälä1-1/+1
2024-05-27drm/i915: Bury c8_planes_changed() in intel_color_check()Ville Syrjälä1-1/+10
2024-05-27drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check()Ville Syrjälä1-0/+5
2024-05-27drm/i915: Plumb the entire atomic state into intel_color_check()Ville Syrjälä1-46/+65
2024-05-24drm/i915: pass dev_priv explicitly to PIPEGCMAXJani Nikula1-6/+6
2024-05-24drm/i915: pass dev_priv explicitly to DSPCNTRJani Nikula1-1/+1
2024-05-22drm/i915: Extract i9xx_plane_regs.hVille Syrjälä1-1/+1
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C22Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C21_C20Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C12Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C11_C10Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C02Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C01_C00Jani Nikula1-2/+2
2024-04-30drm/i915: pass dev_priv explicitly to PALETTEJani Nikula1-10/+19
2024-02-09drm/i915/color: Use per-device debugsVille Syrjälä1-5/+6
2023-11-23drm/i915: Fix glk+ degamma LUT conversionsVille Syrjälä1-26/+28
2023-11-23drm/i915: s/clamp()/min()/ in i965_lut_11p6_max_pack()Ville Syrjälä1-1/+1
2023-11-23drm/i915: Adjust LUT rounding rulesVille Syrjälä1-8/+6
2023-10-13drm/i915/dsb: Re-instate DSB for LUT updatesVille Syrjälä1-3/+0
2023-10-10drm/i915: Fix VLV color state readoutVille Syrjälä1-0/+1
2023-09-27drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä1-1/+1
2023-09-27drm/i915/dsb: Use non-posted register writes for legacy LUTVille Syrjälä1-0/+11
2023-09-27drm/i915/dsb: Load LUTs using the DSB during vblankVille Syrjälä1-6/+24
2023-09-27drm/i915/dsb: Don't use DSB to load the LUTs during full modesetVille Syrjälä1-0/+4
2023-09-07drm/i915: Constify LUT entries in checkerVille Syrjälä1-5/+5
2023-08-25drm/i915/color: move pre-SKL gamma and CSC enable read to intel_colorJani Nikula1-0/+25
2023-08-25drm/i915/color: move SKL+ gamma and CSC enable read to intel_colorJani Nikula1-4/+22
generated by cgit v1.2.3 (git 2.39.1) at 2026-01-06 13:27:12 +0000