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path: root/drivers/gpu/drm/i915/display/intel_dpll.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-05-20drm/i915/dpll: Rename crtc_get_shared_dpllSuraj Kandpal1-2/+2
2025-03-28drm/i915/dpll: convert intel_dpll.[ch] to struct intel_displayJani Nikula1-7/+6
2025-02-12drm/i915/dpll: Use intel_display for asserting pllSuraj Kandpal1-2/+3
2024-04-17drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä1-1/+1
2024-04-17drm/i915: s/pipe_config/crtc_state/ in legacy PLL codeVille Syrjälä1-3/+3
2024-04-17drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()Ville Syrjälä1-6/+3
2024-04-17drm/i915: Extract i9xx_dpll_get_hw_state()Ville Syrjälä1-0/+3
2023-11-17drm/i915: move *_crtc_clock_get() to intel_dpll.cJani Nikula1-2/+7
2022-04-25drm/i915: Add crtc .crtc_get_shared_dpll()Ville Syrjälä1-0/+2
2022-04-25drm/i915: Adjust .crtc_compute_clock() calling conventionVille Syrjälä1-1/+3
2022-02-09drm/i915/dpll: add intel_dpll_crtc_compute_clock()Jani Nikula1-0/+1
2021-10-01drm/i915/dpll: move dpll modeset asserts to intel_dpll.cJani Nikula1-0/+3
2021-08-25drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()Ville Syrjälä1-5/+4
2021-08-25drm/i915: Clean dpll calling conventionVille Syrjälä1-14/+7
2021-08-25drm/i915: Constify struct dpll all overVille Syrjälä1-0/+1
2021-04-28drm/i915/display: move crtc and dpll declarations where they belongJani Nikula1-0/+5
2021-02-08drm/i915: migrate pll enable/disable code to intel_dpll.[ch]Dave Airlie1-0/+18
2021-01-16drm/i915: refactor pll code out into intel_dpll.cDave Airlie1-0/+23
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