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path: root/drivers/gpu/drm/i915/display/intel_lt_phy.c
AgeCommit message (Expand)AuthorLines
2026-01-05drm/i915/ltphy: Provide protection against unsupported modesSuraj Kandpal-1/+6
2026-01-05drm/i915/ltphy: Compare only certain fields in state verify functionSuraj Kandpal-6/+11
2026-01-05drm/i915/ltphy: Remove state verification for LT PHY fieldsSuraj Kandpal-23/+7
2025-12-01drm/i915/power: convert intel_wakeref_t to struct ref_tracker *Jani Nikula-7/+7
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola-2/+2
2025-11-13drm/i915/ltphy: include intel_display_utils.h instead of i915_utils.hJani Nikula-1/+1
2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()Ville Syrjälä-15/+15
2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_us()Ville Syrjälä-9/+9
2025-11-11drm/i915/de: Use intel_de_wait_ms() for the obvious casesVille Syrjälä-17/+15
2025-11-11drm/i915/de: Use intel_de_wait_us()Ville Syrjälä-10/+9
2025-11-11drm/i915/de: Include units in intel_de_wait*() function namesVille Syrjälä-3/+3
2025-11-10drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithmSuraj Kandpal-4/+10
2025-11-10drm/i915/ltphy: Implement HDMI Algo for Pll stateSuraj Kandpal-2/+329
2025-11-07drm/i915/ltphy: Nuke bogus weird timeoutsVille Syrjälä-6/+5
2025-11-07drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/Ville Syrjälä-1/+1
2025-11-07drm/i915/ltphy: Nuke extraneous timeout debugsVille Syrjälä-18/+16
2025-11-01drm/i915/ltphy: Modify the step that need to be skippedSuraj Kandpal-30/+33
2025-11-01drm/i915/ltphy: Define LT PHY PLL state verify functionSuraj Kandpal-0/+56
2025-11-01drm/i915/ltphy: Define function to readout LT Phy PLL stateSuraj Kandpal-0/+33
2025-11-01drm/i915/ltphy: Define the LT Phy state compare functionSuraj Kandpal-0/+30
2025-11-01drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequenceSuraj Kandpal-0/+87
2025-11-01drm/i915/ltphy: Program LT Phy Voltage SwingSuraj Kandpal-0/+63
2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal-0/+21
2025-11-01drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequenceSuraj Kandpal-0/+78
2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal-0/+28
2025-11-01drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL stepsSuraj Kandpal-0/+25
2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal-0/+117
2025-11-01drm/i915/ltphy: Add function to calculate LT PHY port clockSuraj Kandpal-0/+92
2025-11-01drm/i915/ltphy: Enable SSC during port clock programmingSuraj Kandpal-0/+26
2025-11-01drm/i915/ltphy: Update the ltpll config table value for eDPSuraj Kandpal-0/+4
2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal-0/+38
2025-11-01drm/i915/ltphy: Add LT Phy Programming recipe tablesSuraj Kandpal-0/+992
2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal-23/+121
2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal-0/+13
2025-11-01drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT PhySuraj Kandpal-0/+37
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal-0/+159
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