summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/imx/dc
AgeCommit message (Collapse)AuthorLines
2026-01-16drm: Discard pm_runtime_put() return valueRafael J. Wysocki-9/+3
Multiple DRM drivers use the pm_runtime_put() return value for printing debug or even error messages and all of those messages are at least somewhat misleading. Returning an error code from pm_runtime_put() merely means that it has not queued up a work item to check whether or not the device can be suspended and there are many perfectly valid situations in which that can happen, like after writing "on" to the devices' runtime PM "control" attribute in sysfs for one example. It also happens when the kernel has been configured with CONFIG_PM unset. For this reason, modify all of those drivers to simply discard the pm_runtime_put() return value which is what they should be doing. This will facilitate a planned change of the pm_runtime_put() return type to void in the future. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://patch.msgid.link/2256082.irdbgypaU6@rafael.j.wysocki
2025-10-16drm/imx: dc: Sort bits and bitfields in descending orderMarek Vasut-27/+27
Consistently sort bits and bitfields from highest to lowest bits. No functional change. Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20251014114148.43922-1-marek.vasut@mailbox.org
2025-10-06drm/imx-dc: Switch to drm_atomic_get_new_crtc_state()Maxime Ripard-1/+1
The imx-dc atomic_check implementation uses the deprecated drm_atomic_get_existing_crtc_state() helper. This hook is called as part of the global atomic_check, thus before the states are swapped. The existing state thus points to the new state, and we can use drm_atomic_get_new_crtc_state() instead. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20250930-drm-no-more-existing-state-v5-17-eeb9e1287907@kernel.org Signed-off-by: Maxime Ripard <mripard@kernel.org>
2025-05-14drm/imx: Add i.MX8qxp Display Controller KMSLiu Ying-2/+1340
i.MX8qxp Display Controller(DC) is comprised of three main components that include a blit engine for 2D graphics accelerations, display controller for display output processing, as well as a command sequencer. Add kernel mode setting support for the display controller part with two CRTCs and two primary planes(backed by FetchLayer and FetchWarp respectively). The registers of the display controller are accessed without command sequencer involved, instead just by using CPU. The command sequencer is supposed to be used by the blit engine. Reviewed-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20250414035028.1561475-13-victor.liu@nxp.com
2025-05-14drm/imx: Add i.MX8qxp Display Controller interrupt controllerLiu Ying-1/+286
i.MX8qxp Display Controller has a built-in interrupt controller to support Enable/Status/Preset/Clear interrupt bit. Add driver for it. Reviewed-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20250414035028.1561475-12-victor.liu@nxp.com
2025-05-14drm/imx: Add i.MX8qxp Display Controller pixel engineLiu Ying-1/+1868
i.MX8qxp Display Controller pixel engine consists of all processing units that operate in the AXI bus clock domain. Add drivers for ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as well as a pixel engine driver, so that two displays with primary planes can be supported. The pixel engine driver and those unit drivers are components to be aggregated by a master registered in the upcoming DRM driver. Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250414035028.1561475-11-victor.liu@nxp.com
2025-05-14drm/imx: Add i.MX8qxp Display Controller display engineLiu Ying-0/+851
i.MX8qxp Display Controller display engine consists of all processing units that operate in a display clock domain. Add minimal feature support with FrameGen and TCon so that the engine can output display timings. The FrameGen driver, TCon driver and display engine driver are components to be aggregated by a master registered in the upcoming DRM driver. Reviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250414035028.1561475-10-victor.liu@nxp.com