summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/dsi/pll
AgeCommit message (Expand)AuthorLines
2021-04-07drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* codeDmitry Baryshkov-4375/+0
2021-03-17drm/msm/dsi_pll_7nm: Fix variable usage for pll_lockdet_rateDmitry Baryshkov-1/+1
2021-03-17drm/msm/dsi_pll_7nm: Solve TODO for multiplier frac_bits assignmentDmitry Baryshkov-2/+2
2021-03-17drm/msm/dsi: fix check-before-set in the 7nm dsi_pll codeDmitry Baryshkov-5/+8
2021-02-01drm/msm/dsi_pll_10nm: Convert pr_err prints to DRM_DEV_ERRORAngeloGioacchino Del Regno-4/+6
2021-02-01drm/msm/dsi_pll_10nm: Fix variable usage for pll_lockdet_rateAngeloGioacchino Del Regno-1/+2
2021-02-01drm/msm/dsi_pll_10nm: Solve TODO for multiplier frac_bits assignmentAngeloGioacchino Del Regno-2/+2
2021-02-01drm/msm/dsi_pll_10nm: Fix dividing the same numbers twiceAngeloGioacchino Del Regno-3/+1
2020-11-04drm/msm/dsi: do not try reading 28nm vco rate if it's not enabledDmitry Baryshkov-1/+4
2020-11-04drm/msm/dsi_pll_10nm: restore VCO rate during restore_stateDmitry Baryshkov-0/+8
2020-11-04drm/msm/dsi_pll_7nm: restore VCO rate during restore_stateDmitry Baryshkov-0/+8
2020-09-29drm/msm: fix 32b build warnsRob Clark-1/+1
2020-09-12drm/msm/dsi: add support for 7nm DSI PHY/PLLJonathan Marek-0/+918
2020-02-13drm/msm/dsi/pll: call vco set rate explicitlyHarigovindan P-0/+6
2020-01-06clk: mux: Add support for specifying parents via DT/pointersStephen Boyd-4/+4
2019-09-03drm/msm: drop use of drmP.hSam Ravnborg-1/+1
2019-06-28Merge tag 'drm-msm-next-2019-06-25' of https://gitlab.freedesktop.org/drm/msm...Dave Airlie-33/+73
2019-06-20drm/msm/dsi_pll_10nm: Remove impossible checkSean Paul-3/+0
2019-06-20drm/msm/dsi_pll_10nm: Release clk hw on destroy and failureSean Paul-30/+73
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner-45/+5
2018-12-25Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drmLinus Torvalds-28/+28
2018-12-11drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driverAbhinav Kumar-4/+4
2018-12-11drm: msm: Use DRM_DEV_* instead of dev_*Mamta Shukla-24/+24
2018-11-30drm/msm/dsi: configure VCO rate for 10nm PLL driverAbhinav Kumar-1/+3
2018-07-26drm/msm/dsi: initialize postdiv_lock before use for 10nm pllRajesh Yadav-0/+2
2018-02-20drm/msm/dsi: Populate PLL 10nm clock opsArchit Taneja-8/+654
2018-02-20drm/msm/dsi: Add skeleton 10nm PHY/PLL codeArchit Taneja-0/+188
2018-02-20drm/msm/dsi: check for failure on retrieving pll in dsi managerLloyd Atkinson-1/+1
2017-12-28clk: divider: fix incorrect usage of container_ofJerome Brunet-1/+1
2017-02-06drm/msm/dsi: Add PHY/PLL for 8x96Archit Taneja-0/+1127
2016-11-02drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocksArchit Taneja-0/+2
2016-03-03drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()Luis Henriques-2/+2
2015-12-14drm/msm/dsi: Add DSI PLL for 28nm 8960 PHYArchit Taneja-0/+546
2015-09-04Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds-36/+46
2015-08-24drm/msm/dsi: Convert to clk_hw based provider APIsStephen Boyd-2/+2
2015-08-15drm/msm/dsi: Make each PHY type compilation independentHai Li-0/+8
2015-08-15drm/msm/dsi: Save/Restore PLL status across PHY resetHai Li-36/+38
2015-06-11drm/msm/dsi: Add DSI PLL clock driver supportHai Li-0/+905
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-28 05:52:21 +0000