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path: root/drivers/gpu/drm/msm/registers/display
AgeCommit message (Expand)AuthorLines
2025-09-02drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfieldsKrzysztof Kozlowski-1/+10
2025-08-13drm/msm: update the high bitfield of certain DSI registersAyushi Makhija-14/+14
2025-07-04drm/msm/dsi/phy: Add support for SM8750Krzysztof Kozlowski-0/+14
2025-03-05drm/msm/hdmi: update HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE definitionDmitry Baryshkov-1/+1
2025-02-26drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLLKrzysztof Kozlowski-0/+1
2025-02-15drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk sourceKrzysztof Kozlowski-0/+1
2025-02-15drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driverKrzysztof Kozlowski-1/+4
2025-02-15drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver sideKrzysztof Kozlowski-1/+4
2024-12-15drm/msm/mdss: define bitfields for the UBWC_STATIC registerDmitry Baryshkov-1/+10
2024-11-02drm/msm/mdss: use register definitions instead of hand-coding themDmitry Baryshkov-0/+6
2024-11-02drm/msm: move MDSS registers to separate header fileDmitry Baryshkov-16/+23
2024-09-02drm/msm: add msm8998 hdmi phy/pll supportArnaud Vrac-0/+89
2024-04-22drm/msm: import XML display registers databaseDmitry Baryshkov-0/+3974
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