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path: root/drivers/gpu/drm/msm/registers/display (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-09-02drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfieldsKrzysztof Kozlowski1-1/+10
2025-08-13drm/msm: update the high bitfield of certain DSI registersAyushi Makhija1-14/+14
2025-07-04drm/msm/dsi/phy: Add support for SM8750Krzysztof Kozlowski1-0/+14
2025-03-05drm/msm/hdmi: update HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE definitionDmitry Baryshkov1-1/+1
2025-02-26drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLLKrzysztof Kozlowski1-0/+1
2025-02-15drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk sourceKrzysztof Kozlowski1-0/+1
2025-02-15drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driverKrzysztof Kozlowski1-1/+4
2025-02-15drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver sideKrzysztof Kozlowski1-1/+4
2024-12-15drm/msm/mdss: define bitfields for the UBWC_STATIC registerDmitry Baryshkov1-1/+10
2024-11-02drm/msm/mdss: use register definitions instead of hand-coding themDmitry Baryshkov1-0/+6
2024-11-02drm/msm: move MDSS registers to separate header fileDmitry Baryshkov2-16/+23
2024-09-02drm/msm: add msm8998 hdmi phy/pll supportArnaud Vrac1-0/+89
2024-04-22drm/msm: import XML display registers databaseDmitry Baryshkov14-0/+3974
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-26 12:21:37 +0000