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path: root/drivers/gpu/drm/xe/regs/xe_engine_regs.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-07-25drm/xe/xelp: Add Wa_18022495364Tvrtko Ursulin1-0/+3
2025-05-12drm/xe: Add WA BB to capture active context utilizationUmesh Nerlige Ramappa1-0/+5
2025-03-20drm/xe: Apply Wa_16023105232Vinay Belgaumkar1-0/+4
2025-03-12drm/xe: Add MI_MATH and ALU instruction definitionsMichal Wajdeczko1-0/+4
2025-02-25drm/xe/regs: remove a duplicate definition for RING_CTL_SIZE(size)Mingcong Bai1-1/+0
2025-02-03drm/xe/pxp/uapi: Add userspace and LRC support for PXP-using queuesDaniele Ceraolo Spurio1-0/+1
2024-12-13drm/xe: Initial MSI-X support for HW enginesIlia Levi1-0/+3
2024-10-09drm/xe/xe3: Add initial set of workaroundsGustavo Sousa1-0/+1
2024-07-31drm/xe/xe2: Enable Priority Mem ReadPallavi Mishra1-0/+1
2024-06-18drm/xe/oa: Add OAC supportAshutosh Dixit1-0/+1
2024-06-18drm/xe/oa: Add OAR supportAshutosh Dixit1-0/+1
2024-05-08drm/xe: Dump Indirect Ring State registersNiranjana Vishwanathapura1-0/+4
2024-05-08drm/xe: Add Indirect Ring State supportNiranjana Vishwanathapura1-0/+1
2024-05-08drm/xe: Minor cleanup in LRC handlingNiranjana Vishwanathapura1-2/+2
2024-04-24drm/xe: Add INSTDONE registers to devcoredumpJosé Roberto de Souza1-0/+1
2024-04-08drm/xe: Label RING_CONTEXT_CONTROL as maskedAshutosh Dixit1-1/+1
2024-03-08drm/xe: Remove unused FF_SLICE_CS_CHICKEN2Lucas De Marchi1-3/+0
2023-12-26drm/xe/xe2: Add workaround 16020183090Lucas De Marchi1-0/+4
2023-12-21drm/xe: Define registers used by memory based irq processingMichal Wajdeczko1-0/+2
2023-12-21drm/xe: Move engine base offsets to engine register headerMatt Roper1-0/+33
2023-12-21drm/xe: Fix whitespace in register definitionsMatt Roper1-2/+2
2023-12-21drm/xe: Move some per-engine register definitions to the engine headerMatt Roper1-0/+21
2023-12-21drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1Matt Roper1-5/+4
2023-12-21drm/xe: Remove duplicate RING_MAX_NONPRIV_SLOTS definitionMatt Roper1-1/+0
2023-12-21drm/xe/xe2: Add workaround 18032095049 and 16021639441Tejas Upadhyay1-0/+5
2023-12-21drm/xe/xe2: Add workaround 14019449301Tejas Upadhyay1-0/+3
2023-12-21drm/xe/xelpmp: Add Wa_16021867713Gustavo Sousa1-0/+3
2023-12-21drm/xe: Remove devcoredump readout of IPEIRJosé Roberto de Souza1-2/+0
2023-12-21drm/xe: Fix devcoredump readout of IPEHRJosé Roberto de Souza1-1/+0
2023-12-21drm/xe/pvc: Force even num engines to use 64BNiranjana Vishwanathapura1-0/+1
2023-12-21drm/xe/pvc: Blacklist BCS_SWCTRL registerNiranjana Vishwanathapura1-0/+2
2023-12-21drm/xe: enable idle msg and set hysteresis for GSCCSDaniele Ceraolo Spurio1-0/+4
2023-12-19drm/xe: Set default MOCS value for copy cs instructionsJosé Roberto de Souza1-0/+6
2023-12-19drm/xe: Set default MOCS value for cs instructionsJosé Roberto de Souza1-0/+12
2023-12-19drm/xe: Annotate masked registers used by RTPLucas De Marchi1-1/+1
2023-12-19drm/xe: Use XE_REG/XE_REG_MCRLucas De Marchi1-37/+37
2023-12-19drm/xe: Use REG_FIELD/REG_BIT for all regs/*.hLucas De Marchi1-12/+12
2023-12-19drm/xe: Drop gen afixes from registersLucas De Marchi1-4/+4
2023-12-19drm/xe: Fix print of RING_EXECLIST_SQ_CONTENTS_HIRodrigo Vivi1-1/+2
2023-12-19drm/xe: Do not spread i915_reg_defs.h includeLucas De Marchi1-1/+1
2023-12-19drm/xe: Remove dependency on intel_engine_regs.hLucas De Marchi1-0/+98
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