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path: root/drivers/gpu/drm/xe/regs/xe_gt_regs.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-10-13drm/xe: Enable media sampler power gatingVinay Belgaumkar1-0/+1
2025-09-05drm/xe/xe2hpg: Add Wa_18041344222 for Xe2_HPGHarish Chegondi1-0/+1
2025-07-24drm/xe: Rename MCFG_MCR_SELECTOR to STEER_SEMAPHORENitin Gote1-1/+1
2025-05-12drm/xe/xe2hpg: Add Wa_22021007897Aradhya Bhatia1-0/+1
2025-04-09drm/xe: remove unused LE_COSShuicheng Lin1-1/+0
2025-04-04drm/xe/xe2hpg: Add Wa_16025250150Aradhya Bhatia1-0/+12
2025-02-28drm/xe/xelp: L3 recommended hashing maskTvrtko Ursulin1-1/+3
2025-02-28drm/xe/xe3lpg: Add Wa_13012615864Tejas Upadhyay1-0/+1
2025-02-24drm/xe: Add engine activity supportRiana Tauro1-0/+2
2025-01-15drm/xe/xe3: Generate and store the L3 bank maskFrancois Dugast1-0/+3
2025-01-13drm/xe/ptl: Apply Wa_14023061436Nirmoy Das1-0/+3
2024-11-27drm/xe/xe3lpg: Add Wa_16024792527Apoorva Singh1-0/+2
2024-11-01drm/xe: Set mask bits for CCS_MODE registerBalasubramani Vivekanandan1-1/+1
2024-10-09drm/xe/xe3: Add initial set of workaroundsGustavo Sousa1-0/+3
2024-10-09drm/xe/bmg: improve cache flushing behaviourMatthew Auld1-3/+0
2024-10-08drm/xe/guc: Prepare GuC register list and update ADS size for error captureZhanjun Dong1-0/+2
2024-09-26drm/xe: Move IRQ-related registers to dedicated headerMatt Roper1-58/+0
2024-09-23drm/xe/xe2: Add performance tuning for L3 cache flushingGustavo Sousa1-0/+5
2024-09-23drm/xe/xe2: Extend performance tuning to media GTGustavo Sousa1-0/+6
2024-09-11drm/xe/xe2hpg: Add Wa_15016589081Tejas Upadhyay1-0/+1
2024-09-06drm/xe/xe_gt_idle: add debugfs entry for powergating infoRiana Tauro1-0/+8
2024-08-14drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr registerTejas Upadhyay1-1/+1
2024-08-14drm/xe: Write all slices if its mcr registerTejas Upadhyay1-1/+1
2024-08-12drm/xe/xe2hpg: Add Wa_14021821874Tejas Upadhyay1-0/+1
2024-08-06drm/xe/xe2: Add performance turning changesShekhar Chauhan1-0/+4
2024-08-02drm/xe/xe2: Introduce performance changesAkshata Jahagirdar1-0/+3
2024-07-29drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPGSai Teja Pottumuttu1-0/+1
2024-07-05drm/xe/bmg: implement Wa_16023588340Matthew Auld1-0/+8
2024-07-04drm/xe: Kill regs/xe_sriov_regs.hMichal Wajdeczko1-0/+6
2024-06-26Merge drm/drm-next into drm-xe-nextRodrigo Vivi1-0/+3
2024-06-19Merge drm/drm-next into drm-intel-nextJani Nikula1-6/+61
2024-06-18drm/xe/oa: OA stream initialization (OAG)Ashutosh Dixit1-0/+3
2024-06-07drm/xe: Cleanup force wake registers bit definitionsHimal Prasad Ghimiray1-3/+5
2024-05-28drm/xe: Enable Coarse Power GatingRiana Tauro1-0/+4
2024-05-28drm/xe: Standardize power gate registersRiana Tauro1-5/+3
2024-05-08drm/xe/xe2: Add workaround 14021402888Bommu Krishnaiah1-0/+1
2024-05-06drm/xe/mocs: Add debugfs node to dump mocsJanga Rahul Kumar1-1/+37
2024-05-03drm/xe/device: implement transient flushNirmoy Das1-0/+3
2024-04-24drm/xe: Add INSTDONE registers to devcoredumpJosé Roberto de Souza1-0/+13
2024-04-24drm/xe: Add few more GT register definitionsMichal Wajdeczko1-0/+3
2024-04-15drm/xe/gt: Add L3 bank mask to GT topologyFrancois Dugast1-0/+3
2024-04-09drm/xe/xe2hpm: Add initial set of workaroundsGustavo Sousa1-0/+4
2024-04-09drm/xe/xe2hpg: Add initial GT workaroundsHaridhar Kalvala1-0/+5
2024-04-09drm/xe/xe2hpg: Determine flat ccs offset for vramHimal Prasad Ghimiray1-0/+5
2024-04-02drm/xe/xe2: Add workaround 18033852989Himal Prasad Ghimiray1-1/+2
2024-03-28drm/xe/gsc: Implement WA 14018094691Daniele Ceraolo Spurio1-0/+3
2024-03-20drm/xe/xelpg: Add Wa_14020495402Radhakrishna Sripada1-0/+1
2024-03-15drm/xe: Mark VF accessible interrupt registersMichal Wajdeczko1-17/+23
2024-03-14drm/xe/gsc: Handle GSCCS ER interruptDaniele Ceraolo Spurio1-0/+1
2024-02-06drm/xe/hwmon: Refactor xe hwmonKarthik Poosa1-6/+0
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