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2026-02-21Convert more 'alloc_obj' cases to default GFP_KERNEL argumentsLinus Torvalds-2/+1
This converts some of the visually simpler cases that have been split over multiple lines. I only did the ones that are easy to verify the resulting diff by having just that final GFP_KERNEL argument on the next line. Somebody should probably do a proper coccinelle script for this, but for me the trivial script actually resulted in an assertion failure in the middle of the script. I probably had made it a bit _too_ trivial. So after fighting that far a while I decided to just do some of the syntactically simpler cases with variations of the previous 'sed' scripts. The more syntactically complex multi-line cases would mostly really want whitespace cleanup anyway. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21Convert 'alloc_flex' family to use the new default GFP_KERNEL argumentLinus Torvalds-6/+6
This is the exact same thing as the 'alloc_obj()' version, only much smaller because there are a lot fewer users of the *alloc_flex() interface. As with alloc_obj() version, this was done entirely with mindless brute force, using the same script, except using 'flex' in the pattern rather than 'objs*'. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21Convert 'alloc_obj' family to use the new default GFP_KERNEL argumentLinus Torvalds-16/+16
This was done entirely with mindless brute force, using git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' | xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/' to convert the new alloc_obj() users that had a simple GFP_KERNEL argument to just drop that argument. Note that due to the extreme simplicity of the scripting, any slightly more complex cases spread over multiple lines would not be triggered: they definitely exist, but this covers the vast bulk of the cases, and the resulting diff is also then easier to check automatically. For the same reason the 'flex' versions will be done as a separate conversion. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21treewide: Replace kmalloc with kmalloc_obj for non-scalar typesKees Cook-24/+24
This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook <kees@kernel.org>
2026-01-31i3c: dw-i3c-master: fix SIR reject bit mapping for dynamic addressesAdrian Ng Ho Yin-2/+23
The IBI_SIR_REQ_REJECT register is a 32-bit bitmap indexed by the dynamic address of each I3C slave. The DesignWare controller derives the bit index by folding the 7-bit dynamic address into a 5-bit value, using the sum of the lower 5 bits and the upper 2 bits, modulo 32. The current implementation incorrectly uses the device table index when updating the SIR reject mask, which can result in rejecting or accepting IBIs for the wrong device. Compute the SIR reject bit index directly from the dynamic address, as defined by the controller specification, and use it consistently when updating the reject mask. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/d4ad8161e604156c60327060ad3d339ebf18fe4f.1769479330.git.adrianhoyin.ng@altera.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-31i3c: dw-i3c-master: convert spinlock usage to scoped guardsAdrian Ng Ho Yin-26/+8
Convert dw-i3c-master to use scoped spinlock guards in place of open-coded spin_lock_irqsave()/spin_unlock_irqrestore() pairs to ensure locks are always safely released on scope exit. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/79020c006c15dda9d057946530f16cfb4650d450.1769479330.git.adrianhoyin.ng@altera.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-31i3c: dw: Fix memory leak in dw_i3c_master_i2c_xfers()Zilin Guan-0/+1
The dw_i3c_master_i2c_xfers() function allocates memory for the xfer structure using dw_i3c_master_alloc_xfer(). If pm_runtime_resume_and_get() fails, the function returns without freeing the allocated xfer, resulting in a memory leak. Add a dw_i3c_master_free_xfer() call to the error path to ensure the allocated memory is properly freed. Compile tested only. Issue found using a prototype static analysis tool and code review. Fixes: 62fe9d06f570 ("i3c: dw: Add power management support") Signed-off-by: Zilin Guan <zilin@seu.edu.cn> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260126081121.644099-1-zilin@seu.edu.cn Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-31i3c: mipi-i3c-hci-pci: Add System Suspend supportAdrian Hunter-0/+7
Assign the driver PM operations pointer, which is necessary for the PCI subsystem to put the device into a low power state. Refer to pci_pm_suspend_noirq() which bails out if the pointer is NULL, before it has the opportunity to call pci_prepare_to_sleep(). No other actions are necessary as the mipi-i3c-hci driver takes care of controller state. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260123063325.8210-4-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-31i3c: mipi-i3c-hci: Add optional System Suspend supportAdrian Hunter-0/+49
Add system suspend callbacks. Implement them by forcing runtime PM. Consequently bail out if Runtime PM is not allowed. On resume from System Suspend (suspend to RAM), rerun Dynamic Address Assignment to restore addresses for devices that may have lost power. On resume from System Hibernation (suspend to disk), use the new i3c_master_do_daa_ext() helper with 'rstdaa' set to true, which additionally handles the case where devices are assigned different dynamic addresses after a hibernation boot. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260123063325.8210-3-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-31i3c: dw: Initialize spinlock to avoid upsetting lockdepFredrik Markstrom-0/+2
The devs_lock spinlock introduced when adding support for ibi:s was never initialized. Fixes: e389b1d72a624 ("i3c: dw: Add support for in-band interrupts") Suggested-by: Jani Nurminen <jani.nurminen@windriver.com> Signed-off-by: Fredrik Markstrom <fredrik.markstrom@est.tech> Reviewed-by: Ivar Holmqvist <ivar.holmqvist@est.tech> Link: https://patch.msgid.link/20260116-i3c_dw_initialize_spinlock-v3-1-cf707b6ed75f@est.tech Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Add Runtime PM supportAdrian Hunter-0/+17
Enable Runtime PM for the mipi_i3c_hci_pci driver. Introduce helpers to allow and forbid Runtime PM during probe and remove, using pm_runtime APIs. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-22-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Add optional Runtime PM supportAdrian Hunter-6/+72
Implement optional Runtime PM support for the MIPI I3C HCI driver. Introduce runtime suspend and resume callbacks to manage bus state and restore hardware configuration after resume. Optionally enable autosuspend with a default delay of 1 second, and add helper functions to control Runtime PM during probe and remove. Read quirks from i3c_hci_driver_ids[] and set new quirk HCI_QUIRK_RPM_ALLOWED for intel-lpss-i3c devices to enable runtime PM for them. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-21-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Factor out master dynamic address setting into helperAdrian Hunter-3/+10
Prepare for future reuse. Move master dynamic address setting logic from i3c_hci_bus_init() into a dedicated helper function, i3c_hci_set_master_dyn_addr(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-19-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Allow core re-initialization for Runtime PM supportAdrian Hunter-17/+21
Prepare i3c_hci_reset_and_init() to support runtime resume. Update it to handle the case where the I/O mode has already been selected. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-18-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Factor out core initialization into helperAdrian Hunter-67/+75
Prepare for future reuse. Move core initialization logic from i3c_hci_init() into a dedicated helper function, i3c_hci_reset_and_init(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-17-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Factor out IO mode setting into helperAdrian Hunter-14/+31
Prepare for future reuse. Move the IO mode setting logic from i3c_hci_init() into a dedicated helper function, i3c_hci_set_io_mode(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-16-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Factor out software reset into helperAdrian Hunter-12/+29
Prepare for future reuse of the reset sequence in other contexts, such as power management. Move the software reset logic from i3c_hci_init() into a dedicated helper function, i3c_hci_software_reset(). Software reset should never fail. Print an error message if it does. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-15-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Add PIO suspend and resume supportAdrian Hunter-0/+14
Introduce helper functions to suspend and resume PIO operations. These are required to prepare for upcoming Runtime PM support, ensuring that PIO state is properly managed during power transitions. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-14-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Refactor PIO register initializationAdrian Hunter-17/+28
Move the PIO register setup logic out of hci_pio_init() into a new helper, __hci_pio_init(). This refactoring prepares for Runtime PM support by allowing PIO registers to be reinitialized independently after resume. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-13-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Add DMA suspend and resume supportAdrian Hunter-0/+27
Introduce helper functions to suspend and resume DMA operations. These are required to prepare for upcoming Runtime PM support, ensuring that DMA state is properly managed during power transitions. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-12-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Extract ring initialization from hci_dma_init()Adrian Hunter-50/+68
Split the ring setup logic out of hci_dma_init() into a new helper hci_dma_init_rings(). This refactoring prepares for Runtime PM support by allowing DMA rings to be reinitialized independently after resume. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-11-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Introduce helper to restore DATAdrian Hunter-0/+10
Add a dedicated function to restore the Device Address Table (DAT) in preparation for Runtime PM support. This will allow reprogramming the DAT after the controller resumes from a low-power state. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-10-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Cache DAT in memory for Runtime PM restoreAdrian Hunter-6/+29
Prepare for Runtime PM support, which requires restoring the Device Address Table (DAT) registers after resume. Maintain a copy of DAT in memory so it can be reprogrammed when the controller is powered back up. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-9-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Manage DMA deallocation via devres actionAdrian Hunter-2/+21
The driver already uses devres for resource management, but the standard resource-managed DMA allocation helpers cannot be used because they assume the DMA device matches the managed device. To address this, factor out the deallocation logic from hci_dma_cleanup() into a new helper, hci_dma_free(), and register it as a devres action. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-8-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Switch PIO data allocation to devm_kzalloc()Adrian Hunter-3/+1
The driver already uses managed resources, so convert the PIO data structure allocation to devm_zalloc(). Remove the manual kfree(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-7-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Switch DAT bitmap allocation to devm_bitmap_zalloc()Adrian Hunter-11/+3
The driver already uses managed resources, so convert the Device Address Table (DAT) bitmap allocation to use devm_bitmap_zalloc(). Remove the manual cleanup routine. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-6-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Ensure proper bus clean-upAdrian Hunter-3/+39
Wait for the bus to fully disable before proceeding, ensuring that no operations are still in progress. Synchronize the IRQ handler only after interrupt signals have been disabled. This approach also handles cases where bus disable might fail, preventing race conditions and ensuring a consistent shutdown sequence. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-3-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Reset RING_OPERATION1 fields during initAdrian Hunter-0/+8
The MIPI I3C HCI specification does not define reset values for RING_OPERATION1 fields, and some controllers (e.g., Intel) do not clear them during a software reset. Ensure the ring pointers are explicitly set to zero during bus initialization to avoid inconsistent state. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260113072702.16268-2-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: renesas: Add suspend/resume supportTommaso Merciai-0/+89
The Renesas I3C controller does not retain its register state across system suspend, requiring the driver to explicitly save and restore hardware configuration. Add suspend and resume NOIRQ callbacks to handle system sleep transitions. During suspend, save the Device Address Table (DAT) entries, assert reset lines, and disable all related clocks to allow the controller to enter a low-power state. On resume, re-enable clocks and reset lines in the proper order. Restore the REFCKCTL register, master dynamic address, and all DAT entries, then reinitialize the controller. Store the REFCLK divider value, and the master dynamic address to restore timing and addressing configuration after resume. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/c469ef89e0156d37746a85bfc314232847d1185a.1767781092.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: renesas: Factor out hardware initialization to separate functionTommaso Merciai-44/+55
Move the hardware initialization sequence in renesas_i3c_bus_init() into a dedicated renesas_i3c_hw_init() helper. Simplify the code and prepare the driver for upcoming suspend/resume support. No functional change intended. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/795327270a6ceb23e15513a2619a19ae4876cfba.1767781092.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: renesas: Store clock rate and reset controls in struct renesas_i3cTommaso Merciai-19/+20
Update the struct renesas_i3c to store the clock rate, presetn and tresetn handlers. Replace local usage of the clock rate and reset controls with these structure fields. Simplify the code and prepare the driver for upcoming suspend/resume support. No functional change intended. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/9e1da95dd9137590c752ecd9429925afcbeb918b.1767781092.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: renesas: Switch to clk_bulk API and store clocks in private dataTommaso Merciai-33/+13
Replace individual devm_clk_get_enabled() calls with the clk_bulk API and store the clock handles in the driver's private data structure. All clocks required by the controller are now acquired and enabled using devm_clk_bulk_get_all_enabled(), removing the need for per-SoC clock handling and the renesas_i3c_config data. The TCLK is accessed via a fixed index in the bulk clock array. Simplify the code and prepare the driver for upcoming suspend/resume support. No functional change intended. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/1286f8600b542da55facf9920fed7c06b2b0e4d5.1767781092.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Define Multi-Bus instances for supported controllersAdrian Hunter-13/+22
Define Multi-Bus Instances at offset 0x400 for Intel controllers. Intel SoCs include two I3C PCI devices in the Low Power Subsystem (LPSS), each capable of hosting two I3C buses. Panther Lake and Wildcat Lake support three buses in total (IDs 0–2), while Nova Lake supports four (IDs 0–3). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-12-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Add support for Multi-Bus InstancesAdrian Hunter-10/+26
Add support for MIPI I3C Host Controllers with the Multi-Bus Instance capability. These controllers can host multiple I3C buses (up to 15) within a single hardware function (e.g., PCIe B/D/F), providing one indepedent HCI register set and corresponding I3C bus controller logic per bus. Create an MFD cell for each instance and use platform_data to pass the starting address of the instance's register set. The MIPI I3C HCI specification defines an Extended Capability that holds the offset of each instance register set. Parsing this information is relatively complex, so include the offsets in driver data for now. Driver data for additional instances beyond instance 0 will be added in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-11-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Convert to MFD driverAdrian Hunter-35/+41
Prepare for Multi-Bus instance support. Convert to MFD driver but still support only 1 instance. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-10-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Pass base regs as platform data to i3c core deviceAdrian Hunter-19/+20
Use the parent's MMIO mapping for multi-bus instances to avoid overlapping regions. These instances share the same MMIO address space, but the ranges are not guaranteed to be contiguous. By passing base_regs from the parent mapping, child devices can access their registers without creating conflicting mappings. Prepare for multi-bus instance support by passing base_regs to child devices. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-9-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Allow for Multi-Bus InstancesAdrian Hunter-4/+17
Add support for MIPI I3C Host Controllers with the Multi-Bus Instance capability. These controllers can host multiple I3C buses (up to 15) within a single hardware function (e.g., PCIe B/D/F), providing one indepedent HCI register set and corresponding I3C bus controller logic per bus. A separate platform device will represent each instance, but it is necessary to allow for shared resources. Multi-bus instances share the same MMIO address space, but the ranges are not guaranteed to be contiguous. To avoid overlapping mappings, pass base_regs from the parent mapping to child devices. Allow the IRQ to be shared among instances. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-8-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Assign unique device names and IDs for Intel LPSS I3CAdrian Hunter-20/+30
Simplify the code and ensure names and IDs align with device documentation. Use explicit device names and IDs for Intel LPSS I3C controllers instead of dynamically allocated values. Add "intel-lpss-i3c" to the platform_device_id table in the mipi-i3c-hci driver and use the same name for Intel I3C controllers in the mipi_i3c_hci_pci driver. Assign hard-coded IDs to reflect the hardware layout. Intel SoCs include two I3C PCI devices in the Low Power Subsystem (LPSS), each supporting up to two I3C buses. The second PCI device is assigned ID 2 (not 1) to match this topology. Additional IDs will be introduced when Multi-Bus Instance support is implemented. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-7-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Enable MSI supportAdrian Hunter-2/+6
Enable MSI support by using pci_alloc_irq_vectors() to request all supported IRQ types. Do not call pci_free_irq_vectors() because for resource-managed devices (those initialized with pcim_enable_device()), IRQ vector allocation is automatically managed. See pci_setup_msi_context() and pcim_setup_msi_release() for details. Note: The current documentation for pci_alloc_irq_vectors() does not mention this behavior. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-6-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci-pci: Do not repeatedly check for NULL driver_dataAdrian Hunter-3/+3
All entries in the id_table have driver_data. Do not repeatedly check for NULL driver_data. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-5-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Quieten initialization messagesAdrian Hunter-48/+45
The copious initialization messages are at most useful only for debugging. Change them from dev_info() or dev_notice() to dev_dbg(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-4-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Stop reading Extended Capabilities if capability ID is 0Adrian Hunter-1/+1
Extended Capability ID value 0 is special. It signifies the end of the list. Stop reading Extended Capabilities if capability ID is 0. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-3-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: mipi-i3c-hci: Remove duplicate blank linesAdrian Hunter-17/+0
Remove duplicate blank lines from mipi-i3c-hci code. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260106164416.67074-2-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-14i3c: master: svc: Initialize 'dev' to NULL in svc_i3c_master_ibi_isr()Frank Li-2/+2
Initialize the 'dev' pointer to NULL in svc_i3c_master_ibi_isr() and add a NULL check in the error path. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/r/202512131016.YCKIsDXM-lkp@intel.com/ Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251215200852.3079073-1-Frank.Li@nxp.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-13i3c: dw: Preserve DAT entry bits when restoring addressesAdrian Ng Ho Yin-4/+9
Update dw_i3c_master_restore_addrs() to preserve existing bits in each Device Address Table (DAT) entry when restoring addresses. This prevents overwriting configuration bits during PM runtime resumes. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/46112c0da44110f46709cb0e7a4595e312b95c10.1765529948.git.adrianhoyin.ng@altera.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-13i3c: dw: use FIELD_PREP for device address table macrosAdrian Ng Ho Yin-2/+4
Add DEV_ADDR_TABLE_DYNAMIC_MASK / DEV_ADDR_TABLE_DYNAMIC_ADDR(x) for dynamic device addresses and DEV_ADDR_TABLE_STATIC_MASK / DEV_ADDR_TABLE_STATIC_ADDR(x) for static device addresses in the I3C address table. Replace manual shift-and-mask with FIELD_PREP() for both dynamic and static addresses for clarity and maintainability. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/d72896e510db1870d26a794f131f600c7e42cf00.1765529948.git.adrianhoyin.ng@altera.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-01-13i3c: dw: Add support for Device NACK Retry configurationAdrian Ng Ho Yin-0/+40
The DesignWare I3C controller supports automatically retrying transactions when a device NACKs. This is useful for slave devices that may be temporarily busy and not ready to respond immediately. Add new ops to configure all active DAT entry with dev_nack_retry during runtime. Returns error when value exceeds hw specified limit. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/f09ee67e61d31f0a12a0bf48f01e9057ca9e2fb7.1765529948.git.adrianhoyin.ng@altera.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2025-12-12i3c: adi: Fix confusing cleanup.h syntaxKrzysztof Kozlowski-6/+4
Initializing automatic __free variables to NULL without need (e.g. branches with different allocations), followed by actual allocation is in contrary to explicit coding rules guiding cleanup.h: "Given that the "__free(...) = NULL" pattern for variables defined at the top of the function poses this potential interdependency problem the recommendation is to always define and assign variables in one statement and not group variable definitions at the top of the function when __free() is used." Code does not have a bug, but is less readable and uses discouraged coding practice, so fix that by moving declaration to the place of assignment. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251208020750.4727-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2025-12-08i3c: master: switch to use new callback .i3c_xfers() from .priv_xfers()Frank Li-19/+19
Switch to use the new .i3c_xfers() callback, which supports all I3C transfer modes (SDR and HDR). Also replace struct i3c_priv_xfer with the new struct i3c_xfer, as i3c_priv_xfer is now an alias of i3c_xfer. No functional changes. Signed-off-by: Frank Li <Frank.Li@nxp.com> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/20251203-i3c_xfer_cleanup_master-v2-1-7dd94d04ee2d@nxp.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2025-11-29i3c: master: svc: Add basic HDR mode supportFrank Li-13/+83
Add basic HDR mode support for the svs I3C master driver. Only support for private transfers and does not support sending CCC commands in HDR mode. Key differences: - HDR uses commands (0x00-0x7F for write, 0x80-0xFF for read) to distinguish transfer direction. - HDR read/write commands must be written to FIFO before issuing the I3C address command. The hardware automatically sends the standard CCC command to enter HDR mode. - HDR exit pattern must be sent instead of send a stop after transfer completion. - Read/write data size must be an even number. Co-developed-by: Carlos Song <carlos.song@nxp.com> Signed-off-by: Carlos Song <carlos.song@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251106-i3c_ddr-v11-4-33a6a66ed095@nxp.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
generated by cgit v1.2.3 (git 2.46.0) at 2026-03-21 19:26:44 +0000