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2026-04-10mmc: sdhci-msm: Fix the wrapped key handlingNeeraj Soni-5/+0
Inline Crypto Engine (ICE) supports wrapped key generation. While registering crypto profile the supported key types are queried from ICE driver. So the explicit check for RAW key is not needed. Fixes: fd78e2b582a0 ("mmc: sdhci-msm: Add support for wrapped keys") Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-04-09mmc: sdhci-of-dwcmshc: Disable clock before DLL configurationShawn Lin-3/+16
According to the ASIC design recommendations, the clock must be disabled before operating the DLL to prevent glitches that could affect the internal digital logic. In extreme cases, failing to do so may cause the controller to malfunction completely. Adds a step to disable the clock before DLL configuration and re-enables it at the end. Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support") Cc: stable@vger.kernel.org Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: vub300: clean up module initJohan Hovold-17/+16
Clean up module init by dropping redundant error messages (e.g. allocation and USB driver registration failure will already have been logged) and naming error labels after what they do. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: vub300: rename probe error labelsJohan Hovold-8/+10
Error labels should be named after what they do. Rename the probe error labels. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: Merge branch fixes into nextUlf Hansson-7/+12
Merge the mmc fixes for v7.0-rc[n] into the next branch, to allow them to get tested together with the mmc changes that are targeted for the next release. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: vub300: fix use-after-free on disconnectJohan Hovold-6/+11
The vub300 driver maintains an explicit reference count for the controller and its driver data and the last reference can in theory be dropped after the driver has been unbound. This specifically means that the controller allocation must not be device managed as that can lead to use-after-free. Note that the lifetime is currently also incorrectly tied the parent USB device rather than interface, which can lead to memory leaks if the driver is unbound without its device being physically disconnected (e.g. on probe deferral). Fix both issues by reverting to non-managed allocation of the controller. Fixes: dcfdd698dc52 ("mmc: vub300: Use devm_mmc_alloc_host() helper") Cc: stable@vger.kernel.org # 6.17+ Cc: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: vub300: fix NULL-deref on disconnectJohan Hovold-1/+1
Make sure to deregister the controller before dropping the reference to the driver data on disconnect to avoid NULL-pointer dereferences or use-after-free. Fixes: 88095e7b473a ("mmc: Add new VUB300 USB-to-SD/SDIO/MMC driver") Cc: stable@vger.kernel.org # 3.0+ Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: dw_mmc: Remove dw_mci_start_request wrapper and rename core functionShawn Lin-13/+5
The function dw_mci_start_request() was just a thin wrapper around __dw_mci_start_request(). Since it serves almost no functional purpose, remove the wrapper to simplify the code flow. Consequently, rename __dw_mci_start_request() to dw_mci_start_request() so that the core implementation uses the primary name. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: dw_mmc: Inline dw_mci_queue_request() into dw_mci_request()Shawn Lin-27/+19
With the removal of queue support, the function dw_mci_queue_request() is now just a wrapper with a confusing name that doesn't suggest anything about queue. Removes the function and moves its body into dw_mci_request(). No functional changes intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-31mmc: sdhci-dwcmshc: Refactor Rockchip platform data for controller revisionsShawn Lin-35/+57
The driver previously used an enum (dwcmshc_rk_type) to distinguish platforms like the RK3568 and RK3588 based on DT compatible names. This approach is inflexible, scales poorly for future revisions or mixed-revision platforms, and conflates SoC names with controller revisions. One example is RK3576 which lists "rockchip,rk3588-dwcmshc" as a secondary compatible string just in order to claim it uses the same controller revision as RK3588. This is confusing and makes it error-prone to add new SoC support. Introduces a new struct rockchip_pltfm_data containing a dedicated revision field. The old enum is removed, and all code paths are updated to use the revision-based data. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-26mmc: mtk-sd: disable new_tx/rx and modify related settings for mt8189Cathy Xu-5/+5
Disable new_tx/rx to avoid data transmission instability, and adjust .data_tune, .stop_dly_sel, and .pop_en_cnt to fit the overall configuration after disabling new_tx/rx, making it more compatible with mt8189. Fixes: 846a3a2fdff5 ("mmc: mtk-sd: add support for MT8189 SoC") Tested-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-26mmc: sdhci-of-arasan: Use standard mmc_clk_phase_map infrastructureShawn Lin-61/+12
Convert the Arasan SDHCI driver to use the mainline standard mmc_clk_phase_map infrastructure instead of custom clk_phase_in/out arrays as well as arasan_dt_read_clk_phase(). The phase values for ZynqMP, Versal, and Versal-NET platforms are still initialized from the predefined tables. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-25mmc: sdhci-of-aspeed: Handle optional controller resetRyan Chen-0/+6
Get the optional reset line for the ASPEED SD controller during probe by using devm_reset_control_get_optional_exclusive_deasserted(). This allows platforms such as AST2700, which require the SD controller to be taken out of reset before use, to work with the existing driver. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-23mmc: sdhci-pci: Drop unused includeAndy Shevchenko-1/+0
This driver includes the legacy header <linux/gpio.h> but does not use any symbols from it. Drop the inclusion. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-23mmc: sdhci-dwcmshc: Add Canaan K230 DWCMSHC controller supportJiayu Du-0/+260
Add SDHCI controller driver for Canaan k230 SoC. Implement custom sdhci_ops for set_clock, phy init, init and reset. Tested-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-23mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC supportNick Hawkins-0/+146
Add support for the eMMC controller integrated in the HPE GSC (ARM64 Cortex-A53) BMC SoC under the new 'hpe,gsc-dwcmshc' compatible string. The HPE GSC eMMC controller is based on the DesignWare Cores MSHC IP but requires several platform-specific adjustments: Clock mux (dwcmshc_hpe_set_clock): The GSC SoC wires SDHCI_CLOCK_CONTROL.freq_sel directly to a clock mux rather than a divider. Forcing freq_sel = 1 when the requested clock is 200 MHz (HS200) selects the correct high-speed clock source. Using the generic sdhci_set_clock() would otherwise leave the mux on the wrong source after tuning. Auto-tuning / vendor config (dwcmshc_hpe_vendor_specific): Disables the command-conflict check (DWCMSHC_HOST_CTRL3 BIT(0)) and programs the ATCTRL register using existing AT_CTRL_* macros: AT_CTRL_AT_EN auto-tuning circuit enable AT_CTRL_SWIN_TH_EN sampling window threshold enable AT_CTRL_TUNE_CLK_STOP_EN tune-clock-stop enable PRE_CHANGE_DLY = 3 pre-change delay POST_CHANGE_DLY = 3 post-change delay SWIN_TH_VAL = 2 sampling window threshold This combination is required for reliable HS200 signal integrity on the GSC PCB trace topology. eMMC mode (dwcmshc_hpe_set_emmc): Helper that sets DWCMSHC_CARD_IS_EMMC unconditionally. Called from both the reset and UHS-signaling paths. Reset (dwcmshc_hpe_reset): Calls dwcmshc_reset(), re-applies the vendor config above via dwcmshc_hpe_vendor_specific(), and then calls dwcmshc_hpe_set_emmc(). The GSC controller clears the CARD_IS_EMMC bit on every reset; leaving it clear causes card-detect mis-identification on an eMMC-only slot. UHS signaling (dwcmshc_hpe_set_uhs_signaling): Wraps dwcmshc_set_uhs_signaling() and calls dwcmshc_hpe_set_emmc() to ensure CARD_IS_EMMC is set for all timing modes, not just HS400. Init (dwcmshc_hpe_gsc_init): Obtains the SoC register block and MSHCCS offset via the 'hpe,gxp-sysreg' syscon phandle argument and sets SCGSyncDis (BIT(18)) to allow the HS200 RX delay lines to settle while the card clock is stopped during auto-tuning. Enables SDHCI v4 mode. Quirks: SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN: base clock not advertised in capabilities; must be obtained from the DTS 'clocks' property. SDHCI_QUIRK2_PRESET_VALUE_BROKEN: preset-value registers are not populated in the GSC ROM. All HPE-specific code is isolated to the new hpe_gsc_init / hpe_ops / hpe_gsc_pdata symbols. No existing platform (Rockchip, T-Head, sg2042, etc.) is affected. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-23mmc: dw_mmc-pltfm: Use phase_map for SoCFPGA clock phase configurationShawn Lin-7/+8
This change aligns the SoCFPGA driver with the current dw_mmc core, which now manages clock phases through host->phase_map. The phase values are still scaled by SOCFPGA_DW_MMC_CLK_PHASE_STEP before being written to the system manager registers. No functional changes intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-23mmc: sdhci-msm: Add support for wrapped keysNeeraj Soni-1/+41
Add the wrapped key support for sdhci-msm by implementing the needed methods in struct blk_crypto_ll_ops and setting the appropriate flag in blk_crypto_profile::key_types_supported. Tested on SC7280 eMMC variant. How to test: Use the "v1.3.0" tag from https://github.com/google/fscryptctl and build fscryptctl that supports generating wrapped keys. Enable the following config options: CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_QCOM_INLINE_CRYPTO_ENGINE=y CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_MMC_CRYPTO=y Enable "qcom_ice.use_wrapped_keys" via kernel command line. $ mkfs.ext4 -F -O encrypt,stable_inodes /dev/disk/by-partlabel/vm-data $ mount /dev/disk/by-partlabel/vm-data -o inlinecrypt /mnt $ fscryptctl generate_hw_wrapped_key /dev/disk/by-partlabel/vm-data > /mnt/key.longterm $ fscryptctl prepare_hw_wrapped_key /dev/disk/by-partlabel/vm-data < /mnt/key.longterm > /tmp/key.ephemeral $ KEYID=$(fscryptctl add_key --hw-wrapped-key < /tmp/key.ephemeral /mnt) $ rm -rf /mnt/dir $ mkdir /mnt/dir $ fscryptctl set_policy --iv-ino-lblk-32 "$KEYID" /mnt/dir $ dmesg > /mnt/dir/test.txt $ sync Reboot the board $ mount /dev/disk/by-partlabel/vm-data -o inlinecrypt /mnt $ ls /mnt/dir # File should be encrypted $ fscryptctl prepare_hw_wrapped_key /dev/disk/by-partlabel/vm-data < /mnt/key.longterm > /tmp/key.ephemeral $ KEYID=$(fscryptctl add_key --hw-wrapped-key < /tmp/key.ephemeral /mnt) $ fscryptctl set_policy --iv-ino-lblk-32 "$KEYID" /mnt/dir $ cat /mnt/dir/test.txt # File should now be decrypted Tested-by: Wenjia Zhang <wenjia.zhang@oss.qualcomm.com> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: sdhci-pltfm: remove duplicate DTS property parsingLuke Wang-7/+0
The "keep-power-in-suspend", "wakeup-source" and "enable-sdio-wakeup" properties are already parsed in mmc_of_parse(). All sdhci drivers that call sdhci_get_property() also call mmc_of_parse(). The only exception is sdhci-of-hlwd, which does not call mmc_of_parse(), but its devicetree does not use these properties anyway. Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: sdhci-esdhc-imx: remove duplicate HS400 bus width validationLuke Wang-4/+0
mmc_validate_host_caps() already validates that HS400/HS400ES requires 8-bit bus width. Remove the duplicate validation. Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: sdhci-esdhc-imx: add 1-bit bus width supportLuke Wang-2/+2
Add sdhci_get_property() call to parse common SDHCI DT properties, including "bus-width = <1>" which sets SDHCI_QUIRK_FORCE_1_BIT_DATA quirk for 1-bit data bus width configuration. Remove the duplicate "no-1-8-v" property parsing since sdhci_get_property() already handles it. Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: Merge branch fixes into nextUlf Hansson-1/+8
Merge the mmc fixes for v7.0-rc[n] into the next branch, to allow them to get tested together with the mmc changes that are targeted for the next release. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: sdhci: fix timing selection for 1-bit bus widthLuke Wang-1/+8
When 1-bit bus width is used with HS200/HS400 capabilities set, mmc_select_hs200() returns 0 without actually switching. This causes mmc_select_timing() to skip mmc_select_hs(), leaving eMMC in legacy mode (26MHz) instead of High Speed SDR (52MHz). Per JEDEC eMMC spec section 5.3.2, 1-bit mode supports High Speed SDR. Drop incompatible HS200/HS400/UHS/DDR caps early so timing selection falls through to mmc_select_hs() correctly. Fixes: f2119df6b764 ("mmc: sd: add support for signal voltage switch procedure") Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: dw_mmc-rockchip: Add phase map supportShawn Lin-9/+18
Multiple boards require different phase settings, rendering the default phase policy unscalable. Therefore, we introduce phase map to address this limitation. To preserve backward compatibility, the default_sample_phase and original drv phase for different modes are retained, with phase map values taking precedence when available. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: dw_mmc-hi3798mv200: Using phase map from dw_mmc coreShawn Lin-7/+4
dw_mmc core helps parse phase map now, so reuse it. No functional changes intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-16mmc: dw_mmc: Add parsing mmc_clk_phase_map supportShawn Lin-0/+4
The dw_mmc library already assists in invoking mmc_of_parse() to provide unified parsing for variant drivers. We can also call mmc_of_parse_clk_phase() to help variant drivers achieve unified parsing. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: sdhci-esdhc-imx: add NXP S32N79 supportCiprian Marian Costea-0/+9
Add support for the uSDHC controller found in NXP S32N79 automotive SoCs, which reuse the existing sdhci-esdhc-imx driver with slice difference. Compared with s32g2/s32g3, needn't set ESDHC_FLAG_SKIP_CD_WAKE flag because s32n79 does not have this limitation. Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: tifm_sd: Use min3() to simplify tifm_sd_transfer_data()Thorsten Blum-3/+1
Use min3() to simplify tifm_sd_transfer_data(). Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: renesas_sdhi_sys_dmac: Convert to DEFINE_RUNTIME_DEV_PM_OPS()Geert Uytterhoeven-8/+4
Convert the Renesas SDHI SD/SDIO controller driver using SYS-DMAC from an open-coded dev_pm_ops structure to DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr(). This simplifies the code, and reduces kernel size in case CONFIG_PM is disabled. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: loongson2: Add Loongson-2K0300 SD/SDIO/eMMC controller driverBinbin Zhou-0/+27
This patch describes the two MMC controllers of the Loongson-2K0300 SoC, one providing an eMMC interface and the other exporting an SD/SDIO interface. Its hardware design is similar to that of the Loongson-2K2000, but it suffers from hardware defects such as missing CMD48 interrupts. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: loongson2: Gathering all SoCs private data togetherBinbin Zhou-16/+16
More Loongson SoCs will be added, gathering all SoC private data (`loongson2_mmc_pdata`) together to make the code clearer. No functional change intended. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: sdhci-of-bst: Fix memory leak in sdhci_bst_alloc_bounce_buffer()Felix Gu-1/+3
In sdhci_bst_alloc_bounce_buffer(), if dma_alloc_coherent() fails, the function immediately returns -ENOMEM without releasing the reserved memory, which results in a memory leak. Add the missing of_reserved_mem_device_release() call before returning -ENOMEM to properly clean up the reserved memory. Fixes: 695824f45629 ("mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver") Signed-off-by: Felix Gu <ustc.gu@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: Merge the immutable mux branch into nextUlf Hansson-0/+6
The mux branch contains updates to the mux core along with some corresponding changes for a couple of consumer drivers, including an mmc driver. Let's merge it into the next branch to get it tested and queued for the next release. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-09mmc: host: renesas_sdhi_core: support selecting an optional muxJosua Mayer-0/+6
Some hardware designs route data or control signals through a mux to support multiple devices on a single sdhi controller. In particular SolidRun RZ/G2L/G2LC/V2L System on Module use a mux for switching between soldered eMMC and an optional microSD on a carrier board, e.g. for development or provisioning. SD/SDIO/eMMC are not well suited for runtime switching between different cards, however boot-time selection is possible and useful - in particular considering dt overlays. Add support for an optional SD/SDIO/eMMC mux defined in dt, and select it during probe. Similar functionality already exists in other places, e.g. i2c-omap. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-04mmc: Merge branch fixes into nextUlf Hansson-0/+9
Merge the mmc fixes for v7.0-rc[n] into the next branch, to allow them to get tested together with the mmc changes that are targeted for the next release. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-04mmc: sdhci-pci-gli: fix GL9750 DMA write corruptionMatthew Schwartz-0/+9
The GL9750 SD host controller has intermittent data corruption during DMA write operations. The GM_BURST register's R_OSRC_Lmt field (bits 17:16), which limits outstanding DMA read requests from system memory, is not being cleared during initialization. The Windows driver sets R_OSRC_Lmt to zero, limiting requests to the smallest unit. Clear R_OSRC_Lmt to match the Windows driver behavior. This eliminates write corruption verified with f3write/f3read tests while maintaining DMA performance. Cc: stable@vger.kernel.org Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support") Closes: https://lore.kernel.org/linux-mmc/33d12807-5c72-41ce-8679-57aa11831fad@linux.dev/ Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Matthew Schwartz <matthew.schwartz@linux.dev> Reviewed-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-03-04mmc: rtsx_pci_sdmmc: simplify voltage switch handling after card_busy()Ricky Wu-82/+6
Now that the Realtek PCIe SDMMC host implements the card_busy() callback, the MMC core performs the required DAT[3:0] validation during the signal voltage switch sequence. As a result, the driver-side voltage stabilization helpers sd_wait_voltage_stable_1() and sd_wait_voltage_stable_2() become redundant. These helpers duplicate DAT line checks that are now handled centrally by the MMC core via card_busy(). Remove the two stabilization helpers and simplify sdmmc_switch_voltage() accordingly, keeping only the minimal clock control needed around the voltage switch. No functional changes and intended. Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24mmc: sdhci-pic32: allow driver to be compiled with COMPILE_TESTBrian Masney-1/+1
This driver currently only supports builds against a PIC32 target. Now that commit d6618d277c1a ("mmc: sdhci-pic32: update include to use pic32.h from platform_data") is merged, it's possible to compile this driver on other architectures. To avoid future breakage of this driver in the future, let's update the Kconfig so that it can be built with COMPILE_TEST enabled on all architectures. Signed-off-by: Brian Masney <bmasney@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24mmc: sdhci-pic32: add SPDX license identifierBrian Masney-4/+1
Add the missing SPDX license identifier to the top of the file, and drop the boiler plate license text. Signed-off-by: Brian Masney <bmasney@redhat.com> Cc: linux-spdx@vger.kernel.org Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24mmc: dw_mmc: Rename dw_mci_pltfm_pmops to dw_mci_pmopsShawn Lin-7/+7
Since it's moved to dw_mmc core and resued by others variant host drivers, so drop the pltfm notation. Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24mmc: sdhci-of-arasan: add support on Axiado AX3000 SoCSriNavmani A-0/+15
Axiado AX3000 SoC eMMC controller is based on Arasan eMMC 5.1 host controller IP. Signed-off-by: SriNavmani A <srinavmani@axiado.com> Signed-off-by: Tzu-Hao Wei <twei@axiado.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-24mmc: host: Remove unnecessary module_init/exit functionsEthan Nelson-Moore-38/+1
Three MMC drivers have unnecessary module_init and module_exit functions that are empty or just print a message. Remove them. Note that if a module_init function exists, a module_exit function must also exist; otherwise, the module cannot be unloaded. Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: dw_mmc: move pmops into core driverArnd Bergmann-9/+6
Since the platform power management structure is now shared with the PCI front-end, there is a link failure if only the PCI variant is enabled: arm-linux-gnueabi/bin/arm-linux-gnueabi-ld: drivers/mmc/host/dw_mmc-pci.o:(.data+0x74): undefined reference to `dw_mci_pltfm_pmops' This could be fixed by selecting the platform driver from the PCI one in Kconfig, or by reverting the change to the PCI driver, but since this is now used by all dw_mmc variants, just move the structure into the core code as well. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: loongson2-mmc: drop redundant memset after dma_alloc_coherent()Andre Korol-1/+0
dma_alloc_coherent() returns zeroed memory, so the memset() immediately after allocation is redundant. Signed-off-by: Andre Korol <andre.korol.dev@gmail.com> Reviewed-by: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: dw_mmc: Remove mshc alias supportShawn Lin-6/+3
Remove the long-deprecated mshc alias support, as the mmc core already provides alias functionality through the standard mmc alias. This eliminates the redundant dual-alias system. The driver now obtains the controller ID from struct mmc_host::index(supplied by mmc alias) instead of the legacy mshc alias. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: dw_mmc-k3: Remove mshc alias supportShawn Lin-15/+8
Remove the long-deprecated mshc alias support, as the mmc core already provides alias functionality through the standard mmc alias. This eliminates the redundant dual-alias system. The driver now obtains the controller ID from struct mmc_host::index(supplied by mmc alias) instead of the legacy mshc alias. dw_mci_hi6220_parse_dt() which parse mshc alias is used for hi6220, hi3660 and hi3670. Given hi6220 never assigned mshc alias on the DTS files, and hi3360 and hi3670 share the same code, so with it removed, add a return value to dw_mci_hs_set_timing() and let dw_mci_hi3660_init() check if index exceeds TIMING_MODE in the firs place to bail out early, the same as before. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: sdhci: add Black Sesame Technologies BST C1200 controller driverAlbert Yang-0/+536
Add SDHCI controller driver for Black Sesame Technologies C1200 SoC. This driver supports the DWCMSHC SDHCI controller with BST-specific enhancements including: - Custom clock management and tuning - Power management support - BST-specific register configurations - Support for eMMC and SD card interfaces - Hardware limitation workaround for 32-bit DMA addressing The driver addresses specific hardware constraints where: - System memory uses 64-bit bus, eMMC controller uses 32-bit bus - eMMC controller cannot access memory through SMMU due to hardware bug - All system DRAM is configured outside 4GB boundary (ZONE_DMA32) - Uses SRAM-based bounce buffer within 32-bit address space Signed-off-by: Ge Gordon <gordon.ge@bst.ai> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: sdhci: allow drivers to pre-allocate bounce bufferAlbert Yang-0/+7
Allow platform drivers to pre-allocate bounce buffer by checking if host->bounce_buffer is already set before attempting allocation. This enables platforms with specific DMA constraints (such as 32-bit DMA on controllers that cannot access high memory) to use their own reserved memory regions for the bounce buffer. Suggested-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: sdhci-of-k1: spacemit: Add support for K3 SoCYixun Lan-2/+17
The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 generation and introduce a compatible data to denote the change that broken 64BIT DMA issue has been fixed. Signed-off-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2026-02-23mmc: sdhci: Stop advertising the driver in dmesgLinus Walleij-16/+0
As much as we have grown used to seeing this message on every kernel boot, it does not add any technical value. Drop all messages from sdhci_drv_init(), and drop the module_init() and module_exit() calls as well since they now become empty. The modules becomes a pure library module, meaning it will get pulled in by modprobe() when the symbols inside it are needed, or compiled in if any users are compiled in. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-05 01:26:42 +0000