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2025-10-13PCI: cadence: Search for MSI Capability with correct IDHans Zhang1-1/+1
907912c1daa7 ("PCI: cadence: Use cdns_pcie_find_*capability() to avoid hardcoding offsets") incorrectly searched for the MSI-X Capability ID instead of the MSI Capability ID in cdns_pcie_ep_get_msi(). Search for PCI_CAP_ID_MSI, not PCI_CAP_ID_MSIX, to fix this problem. Fixes: 907912c1daa7 ("PCI: cadence: Use cdns_pcie_find_*capability() to avoid hardcoding offsets") Reported-by: Sasha Levin <sashal@kernel.org> Closes: https://lore.kernel.org/r/aOfMk9BW8BH2P30V@laps/ Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251010144307.12979-1-18255117159@163.com
2025-10-03Merge branch 'pci/controller/sophgo'Bjorn Helgaas6-6/+151
- Check for existence of struct cdns_pcie.ops before using it to allow Cadence drivers that don't need to supply ops (Chen Wang) - Add DT binding and driver for the Sophgo SG2042 PCIe controller (Chen Wang) * pci/controller/sophgo: PCI: sg2042: Add Sophgo SG2042 PCIe driver PCI: cadence: Check for the existence of cdns_pcie::ops before using it dt-bindings: pci: Add Sophgo SG2042 PCIe host
2025-10-03Merge branch 'pci/controller/j721e'Bjorn Helgaas1-1/+27
- Add MODULE_DEVICE_TABLE() so driver can be autoloaded (Siddharth Vadapalli) - Power controller off before configuring the glue layer so the controller latches the correct values on power-on (Siddharth Vadapalli) - Correct the error message when j721e_pcie_ctrl_init() fails (Alok Tiwari) * pci/controller/j721e: PCI: j721e: Fix incorrect error message in probe() PCI: j721e: Fix programming sequence of "strap" settings PCI: j721e: Fix module autoloading
2025-10-03Merge branch 'pci/endpoint'Bjorn Helgaas1-2/+0
- Check for errors returned from pci_epc_get(), which returns IS_ERR(), not NULL on error (Dan Carpenter) - Fix pci_endpoint_test_ioctl() array underflow (Dan Carpenter) - Document sysfs interface for BAR assignment of vNTB endpoint functions (Jerome Brunet) - Drop superfluous pci_epc_features initialization for unsupported features; we only have to mention features that *are* supported (Niklas Cassel) - Skip IRQ tests if the IRQ is out of range (Christian Bruel) - Fix pci-epf-test for controllers with fixed-size BARs smaller than requested by the test (Marek Vasut) - Restore inbound translation when disabling doorbell so the doorbell test case can be run more than once (Niklas Cassel) - Check for NULL before releasing DMA channels to avoid a NULL pointer dereference (Shin'ichiro Kawasaki) - Convert tegra194 interrupt number to MSI vector to fix endpoint Kselftest MSI_TEST test case (Niklas Cassel) - Set tegra_pcie_epc_features.msi_capable so the pci_endpoint_test can use the optimal IRQ type (Niklas Cassel) - Reset tegra194 BARs when running in endpoint mode so the BAR tests don't overwrite the ATU settings in BAR4 (Niklas Cassel) - Handle errors in tegra194 BPMP transactions so we don't mistakenly skip future PERST# assertion (Vidya Sagar) * pci/endpoint: PCI: tegra194: Handle errors in BPMP response PCI: tegra194: Reset BARs when running in PCIe endpoint mode PCI: tegra194: Set pci_epc_features::msi_capable to true PCI: tegra194: Fix broken tegra_pcie_ep_raise_msi_irq() PCI: endpoint: pci-epf-test: Add NULL check for DMA channels before release PCI: endpoint: pci-epf-test: Fix doorbell test support PCI: endpoint: pci-epf-test: Limit PCIe BAR size for fixed BARs selftests: pci_endpoint: Skip IRQ test if IRQ is out of range. misc: pci_endpoint_test: Cleanup extra 0 initialization misc: pci_endpoint_test: Skip IRQ tests if irq is out of range PCI: endpoint: Drop superfluous pci_epc_features initialization Documentation: PCI: endpoint: Document BAR assignment misc: pci_endpoint_test: Fix array underflow in pci_endpoint_test_ioctl() PCI: endpoint: pci-ep-msi: Fix NULL vs IS_ERR() check in pci_epf_write_msi_msg()
2025-09-29PCI: j721e: Fix incorrect error message in probe()Alok Tiwari1-1/+1
The probe() function prints "pm_runtime_get_sync failed" when j721e_pcie_ctrl_init() returns an error. This is misleading since the failure is not from pm_runtime, but from the controller init routine. Update the error message to correctly reflect the source. No functional changes. Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver") Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20250905211436.3048282-1-alok.a.tiwari@oracle.com
2025-09-19PCI: sg2042: Add Sophgo SG2042 PCIe driverChen Wang3-0/+145
Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe controller in SG2042 works in host mode only, supporting data rate up to 16 GT/s and lanes up to x16 or x8. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [mani: reworded description and minor code cleanups] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com
2025-09-19PCI: cadence: Check for the existence of cdns_pcie::ops before using itChen Wang3-6/+6
cdns_pcie::ops might not be populated by all the Cadence glue drivers. This is going to be true for the upcoming Sophgo platform which doesn't set the ops. Hence, add a check to prevent NULL pointer dereference. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [mani: reworded subject and description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/35182ee1d972dfcd093a964e11205efcebbdc044.1757643388.git.unicorn_wang@outlook.com
2025-09-08PCI: j721e: Fix programming sequence of "strap" settingsSiddharth Vadapalli1-0/+25
The Cadence PCIe Controller integrated in the TI K3 SoCs supports both Root-Complex and Endpoint modes of operation. The Glue Layer allows "strapping" the Mode of operation of the Controller, the Link Speed and the Link Width. This is enabled by programming the "PCIEn_CTRL" register (n corresponds to the PCIe instance) within the CTRL_MMR memory-mapped register space. The "reset-values" of the registers are also different depending on the mode of operation. Since the PCIe Controller latches onto the "reset-values" immediately after being powered on, if the Glue Layer configuration is not done while the PCIe Controller is off, it will result in the PCIe Controller latching onto the wrong "reset-values". In practice, this will show up as a wrong representation of the PCIe Controller's capability structures in the PCIe Configuration Space. Some such capabilities which are supported by the PCIe Controller in the Root-Complex mode but are incorrectly latched onto as being unsupported are: - Link Bandwidth Notification - Alternate Routing ID (ARI) Forwarding Support - Next capability offset within Advanced Error Reporting (AER) capability Fix this by powering off the PCIe Controller before programming the "strap" settings and powering it on after that. The runtime PM APIs namely pm_runtime_put_sync() and pm_runtime_get_sync() will decrement and increment the usage counter respectively, causing GENPD to power off and power on the PCIe Controller. Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250908120828.1471776-1-s-vadapalli@ti.com
2025-09-01PCI: j721e: Fix module autoloadingSiddharth Vadapalli1-0/+1
Commit a2790bf81f0f ("PCI: j721e: Add support to build as a loadable module") added support to build the driver as a loadable module. However, it did not add MODULE_DEVICE_TABLE() which is required for autoloading the driver based on device table when it is built as a loadable module. Fix it by adding MODULE_DEVICE_TABLE. Fixes: a2790bf81f0f ("PCI: j721e: Add support to build as a loadable module") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> [mani: reworded description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250901120359.3410774-1-s-vadapalli@ti.com
2025-08-20PCI: cadence: Use cdns_pcie_find_*capability() to avoid hardcoding offsetsHans Zhang2-21/+22
The PCI capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Use the cdns_pcie_find_{ext}_capability() APIs to find the capabilities, which avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250813144529.303548-7-18255117159@163.com
2025-08-20PCI: cadence: Implement capability search using PCI core APIsHans Zhang2-0/+48
The PCI core now provides generic PCI_FIND_NEXT_CAP() and PCI_FIND_NEXT_EXT_CAP() macros to search for PCI capabilities, using config accessors we supply. Use them in the CDNS driver to add cdns_pcie_find_capability() and cdns_pcie_find_ext_capability() interfaces. Signed-off-by: Hans Zhang <18255117159@163.com> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250813144529.303548-6-18255117159@163.com
2025-08-14PCI: endpoint: Drop superfluous pci_epc_features initializationNiklas Cassel1-2/+0
struct pci_epc_features has static storage duration, so all struct members are zero initialized implicitly. Thus, remove explicit zero initialization for features that are *not* supported so we don't have to touch existing drivers as new features are added. Signed-off-by: Niklas Cassel <cassel@kernel.org> [bhelgaas: squash together, expand commit log rationale] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> #rcar-ep, rcar-gen4 Link: https://patch.msgid.link/20250814152119.1562063-16-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-17-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-18-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-19-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-20-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-21-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-22-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-23-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-24-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-25-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-26-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-27-cassel@kernel.org Link: https://patch.msgid.link/20250814152119.1562063-28-cassel@kernel.org
2025-06-19PCI: cadence: Replace private message routing enums with PCI core definitionsHans Zhang2-21/+1
The Cadence driver previously defined its own message routing enums (e.g., MSG_ROUTING_LOCAL) and message codes, which duplicated existing PCI core macros (PCIE_MSG_TYPE_R_LOCAL, PCIE_MSG_CODE_ASSERT_INTA, etc.) in drivers/pci/pci.h. These core definitions align with the PCIe r6.0 spec. Remove the driver-specific enums and switch to the centralized PCI core macros. This eliminates redundancy, ensures consistency, and simplifies future updates. No functional changes are introduced. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250607154913.805027-2-18255117159@163.com
2025-06-04Merge branch 'pci/controller/dw-rockchip'Bjorn Helgaas1-5/+1
- Check only PCIE_LINKUP, not LTSSM status, to determine whether the link is up (Shawn Lin) - Increase N_FTS (used in L0s->L0 transitions) and enable ASPM L0s for Root Complex and Endpoint modes (Shawn Lin) - Hide the broken ATS Capability in rockchip_pcie_ep_init() instead of rockchip_pcie_ep_pre_init() so it stays hidden after PERST# resets non-sticky registers (Shawn Lin) - Remove unused PCIE_CLIENT_GENERAL_DEBUG definition (Hans Zhang) - Organize register and bitfield definitions logically (Hans Zhang) - Use rockchip_pcie_link_up() to check link up instead of open coding, and use GENMASK() and FIELD_GET() when possible (Hans Zhang) - Call phy_power_off() before phy_exit() in rockchip_pcie_phy_deinit() (Diederik de Haas) - Return bool (not int) for link-up check in dw_pcie_ops.link_up() and armada8k, dra7xx, dw-rockchip, exynos, histb, keembay, keystone, kirin, meson, qcom, qcom-ep, rcar_gen4, spear13xx, tegra194, uniphier, visconti (Hans Zhang) - Return bool (not int) for link-up check in mobiveil_pab_ops.link_up() and layerscape-gen4, mobiveil (Hans Zhang) - Simplify j721e link-up check (Hans Zhang) - Convert pci-host-common to a library so platforms that don't need native host controller drivers don't need to include these helper functions (Manivannan Sadhasivam) * pci/controller/dw-rockchip: PCI: qcom: Replace PERST# sleep time with proper macro PCI: dw-rockchip: Replace PERST# sleep time with proper macro PCI: host-common: Convert to library for host controller drivers PCI: cadence: Simplify J721e link status check PCI: mobiveil: Return bool from link up check PCI: dwc: Return bool from link up check PCI: dw-rockchip: Fix PHY function call sequence in rockchip_pcie_phy_deinit() PCI: dw-rockchip: Use rockchip_pcie_link_up() to check link up instead of open coding PCI: dw-rockchip: Reorganize register and bitfield definitions PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG definition PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to dw_pcie_ep_ops::init() PCI: dw-rockchip: Enable ASPM L0s capability for both RC and EP modes PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up() # Conflicts: # drivers/pci/controller/pcie-apple.c # include/linux/pci-ecam.h
2025-06-04Merge branch 'pci/controller/cadence'Bjorn Helgaas6-36/+197
- Drop a runtime PM 'put' to resolve a runtime atomic count underflow (Hans Zhang) - Use shared PCIE_MSG_CODE_* definitions and remove duplicate cdns_pcie_msg_code definitions (Hans Zhang) - Make the cadence core buildable as a module (Kishon Vijay Abraham I) - Add cdns_pcie_host_disable() and cdns_pcie_ep_disable() for use by loadable drivers when they are removed (Siddharth Vadapalli) - Make j721e buildable as a loadable and removable module (Siddharth Vadapalli) - Fix j721e host/endpoint dependencies that result in link failures in some configs (Arnd Bergmann) * pci/controller/cadence: PCI: j721e: Fix host/endpoint dependencies PCI: j721e: Add support to build as a loadable module PCI: cadence-ep: Introduce cdns_pcie_ep_disable() helper for cleanup PCI: cadence-host: Introduce cdns_pcie_host_disable() helper for cleanup PCI: cadence: Add support to build pcie-cadence library as a kernel module PCI: cadence: Remove duplicate message code definitions PCI: cadence: Fix runtime atomic count underflow
2025-06-02PCI: j721e: Fix host/endpoint dependenciesArnd Bergmann2-4/+4
The j721e driver has a single platform driver that can be built-in or a loadable module, but it calls two separate backend drivers depending on whether it is a host or endpoint. If the two modes are not the same, we can end up with a situation where the built-in pci-j721e driver tries to call the modular host or endpoint driver, which causes a link failure: ld.lld-21: error: undefined symbol: cdns_pcie_ep_setup >>> referenced by pci-j721e.c >>> drivers/pci/controller/cadence/pci-j721e.o:(j721e_pcie_probe) in archive vmlinux.a ld.lld-21: error: undefined symbol: cdns_pcie_host_setup >>> referenced by pci-j721e.c >>> drivers/pci/controller/cadence/pci-j721e.o:(j721e_pcie_probe) in archive vmlinux.a Rework the dependencies so that the 'select' is done by the common Kconfig symbol, based on which of the two are enabled. Effectively this means that having one built-in makes the other either built-in or disabled, but all configurations will now build. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20250423162523.2060405-1-arnd@kernel.org
2025-06-02PCI: j721e: Add support to build as a loadable moduleSiddharth Vadapalli2-4/+32
The 'pci-j721e.c' driver is the application/glue/wrapper driver for the Cadence PCIe Controllers on TI SoCs. Implement support for building it as a loadable module. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250417124408.2752248-5-s-vadapalli@ti.com
2025-06-02PCI: cadence-ep: Introduce cdns_pcie_ep_disable() helper for cleanupSiddharth Vadapalli2-0/+16
Introduce the helper function cdns_pcie_ep_disable() which will undo the configuration performed by cdns_pcie_ep_setup(). Also, export it for use by the existing callers of cdns_pcie_ep_setup(), thereby allowing them to cleanup on their exit path. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250417124408.2752248-4-s-vadapalli@ti.com
2025-06-02PCI: cadence-host: Introduce cdns_pcie_host_disable() helper for cleanupSiddharth Vadapalli2-0/+109
Introduce the helper function cdns_pcie_host_disable() which will undo the configuration performed by cdns_pcie_host_setup(). Also, export it for use by existing callers of cdns_pcie_host_setup(), thereby allowing them to cleanup on their exit path. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250417124408.2752248-3-s-vadapalli@ti.com
2025-06-02PCI: cadence: Add support to build pcie-cadence library as a kernel moduleKishon Vijay Abraham I5-5/+32
Currently, the Cadence PCIe controller driver can be built as a built-in module only. Since PCIe functionality is not a necessity for booting, add support to build the Cadence PCIe driver as a loadable module as well. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250417124408.2752248-2-s-vadapalli@ti.com
2025-05-28PCI: cadence: Remove duplicate message code definitionsHans Zhang2-13/+3
The Cadence PCIe controller driver defines message codes in enum cdns_pcie_msg_code duplicating the existing PCIE_MSG_CODE_* definitions in drivers/pci/pci.h. The driver only uses ASSERT_INTA and DEASSERT_INTA codes from this enum. Remove the redundant Cadence-specific enum definitions and use the ones available in drivers/pci/pci.h. This helps in avoiding code duplication, maintaining consistency with the spec, and simplifying the code maintenance. Signed-off-by: Hans Zhang <18255117159@163.com> [mani: commit message rewording] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250401145023.22948-1-18255117159@163.com
2025-05-28PCI: endpoint: Align pci_epc_set_msix(), pci_epc_ops::set_msix() nr_irqs ↵Niklas Cassel1-5/+3
encoding The kdoc for pci_epc_set_msix() says: "Invoke to set the required number of MSI-X interrupts." The kdoc for the callback pci_epc_ops->set_msix() says: "ops to set the requested number of MSI-X interrupts in the MSI-X capability register" pci_epc_ops::set_msix() does however expect the parameter 'interrupts' to be in the encoding as defined by the Table Size field. Nowhere in the kdoc does it say that the number of interrupts should be in Table Size encoding. It is very confusing that the API pci_epc_set_msix() and the callback function pci_epc_ops::set_msix() both take a parameter named 'interrupts', but they expect completely different encodings. Clean up the API and the callback function to have the same semantics, i.e. the parameter represents the number of interrupts, regardless of the internal encoding of that value. Also rename the parameter 'interrupts' to 'nr_irqs', in both the wrapper function and the callback function, such that the name is unambiguous. [bhelgaas: more specific subject] Signed-off-by: Niklas Cassel <cassel@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable+noautosel@kernel.org # this is simply a cleanup Link: https://patch.msgid.link/20250514074313.283156-14-cassel@kernel.org
2025-05-28PCI: endpoint: Align pci_epc_set_msi(), pci_epc_ops::set_msi() nr_irqs encodingNiklas Cassel1-1/+2
The kdoc for pci_epc_set_msi() says: "Invoke to set the required number of MSI interrupts." The kdoc for the callback pci_epc_ops::set_msi() says: "ops to set the requested number of MSI interrupts in the MSI capability register" pci_epc_ops::set_msi() does however expect the parameter 'interrupts' to be in the encoding as defined by the Multiple Message Capable (MMC) field of the MSI capability structure. Nowhere in the kdoc does it say that the number of interrupts should be in MMC encoding. It is very confusing that the API pci_epc_set_msi() and the callback function pci_epc_ops::set_msi() both take a parameter named 'interrupts', but they expect completely different encodings. Clean up the API and the callback function to have the same semantics, i.e. the parameter represents the number of interrupts, regardless of the internal encoding of that value. Also rename the parameter 'interrupts' to 'nr_irqs', in both the wrapper function and the callback function, such that the name is unambiguous. [bhelgaas: more specific subject] Signed-off-by: Niklas Cassel <cassel@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable+noautosel@kernel.org # this is simply a cleanup Link: https://patch.msgid.link/20250514074313.283156-13-cassel@kernel.org
2025-05-28PCI: endpoint: Align pci_epc_get_msix(), pci_epc_ops::get_msix() return ↵Niklas Cassel1-1/+1
value encoding The kdoc for pci_epc_get_msix() says: "Invoke to get the number of MSI-X interrupts allocated by the RC" The kdoc for the callback pci_epc_ops->get_msix() says: "ops to get the number of MSI-X interrupts allocated by the RC from the MSI-X capability register" pci_epc_ops::get_msix() does however return the number of interrupts in the encoding as defined by the Table Size field. Nowhere in the kdoc does it say that the returned number of interrupts is in Table Size encoding. It is very confusing that the API pci_epc_get_msix() and the callback function pci_epc_ops::get_msix() don't return the same value. Clean up the API and the callback function to have the same semantics, i.e. return the number of interrupts, regardless of the internal encoding of that value. [bhelgaas: more specific subject] Signed-off-by: Niklas Cassel <cassel@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Cc: stable+noautosel@kernel.org # this is simply a cleanup Link: https://patch.msgid.link/20250514074313.283156-12-cassel@kernel.org
2025-05-28PCI: endpoint: Align pci_epc_get_msi(), pci_epc_ops::get_msi() return value ↵Niklas Cassel1-1/+1
encoding The kdoc for API pci_epc_get_msi() says: "Invoke to get the number of MSI interrupts allocated by the RC" The kdoc for the callback pci_epc_ops::get_msi() says: "ops to get the number of MSI interrupts allocated by the RC from the MSI capability register" pci_epc_ops::get_msi() does however return the number of interrupts in the encoding as defined by the Multiple Message Enable (MME) field of the MSI Capability structure. Nowhere in the kdoc does it say that the returned number of interrupts is in MME encoding. It is very confusing that the API pci_epc_get_msi() and the callback function pci_epc_ops::get_msi() don't return the same value. Clean up the API and the callback function to have the same semantics, i.e. return the number of interrupts, regardless of the internal encoding of that value. [bhelgaas: more specific subject] Signed-off-by: Niklas Cassel <cassel@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Cc: stable+noautosel@kernel.org # this is simply a cleanup Link: https://patch.msgid.link/20250514074313.283156-11-cassel@kernel.org
2025-05-28PCI: cadence-ep: Correct PBA offset in .set_msix() callbackNiklas Cassel1-2/+3
While cdns_pcie_ep_set_msix() writes the Table Size field correctly (N-1), the calculation of the PBA offset is wrong because it calculates space for (N-1) entries instead of N. This results in the following QEMU error when using PCI passthrough on a device which relies on the PCI endpoint subsystem: failed to add PCI capability 0x11[0x50]@0xb0: table & pba overlap, or they don't fit in BARs, or don't align Fix the calculation of PBA offset in the MSI-X capability. [bhelgaas: more specific subject and commit log] Fixes: 3ef5d16f50f8 ("PCI: cadence: Add MSI-X support to Endpoint driver") Signed-off-by: Niklas Cassel <cassel@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250514074313.283156-10-cassel@kernel.org
2025-05-13PCI: cadence: Simplify J721e link status checkHans Zhang1-5/+1
Replace explicit if-else condition with direct return statement in j721e_pcie_link_up(). This reduces code verbosity while maintaining the same logic for detecting PCIe link completion. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Niklas Cassel <cassel@kernel.org> Link: https://patch.msgid.link/20250510160710.392122-4-18255117159@163.com
2025-04-23PCI: cadence: Fix runtime atomic count underflowHans Zhang1-10/+1
If the call to pci_host_probe() in cdns_pcie_host_setup() fails, PM runtime count is decremented in the error path using pm_runtime_put_sync(). But the runtime count is not incremented by this driver, but only by the callers (cdns_plat_pcie_probe/j721e_pcie_probe). And the callers also decrement the runtime PM count in their error path. So this leads to the below warning from the PM core: "runtime PM usage count underflow!" So fix it by getting rid of pm_runtime_put_sync() in the error path and directly return the errno. Fixes: 49e427e6bdd1 ("Merge branch 'pci/host-probe-refactor'") Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250419133058.162048-1-18255117159@163.com
2025-03-27Merge branch 'pci/misc'Bjorn Helgaas1-4/+4
- Remove unused tools 'pci' build target left over after moving tests to tools/testing/selftests/pci_endpoint (Jianfeng Liu) - Fix typos and whitespace errors (Bjorn Helgaas) * pci/misc: PCI: Fix typos tools/Makefile: Remove pci target # Conflicts: # drivers/pci/endpoint/functions/pci-epf-test.c
2025-03-27Merge branch 'pci/controller/j721e'Bjorn Helgaas1-2/+3
- Correct the 'link down' interrupt bit for J784S4 (Siddharth Vadapalli) * pci/controller/j721e: PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4
2025-03-26PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4Siddharth Vadapalli1-2/+3
Commit e49ad667815d ("PCI: j721e: Add TI J784S4 PCIe configuration") assigned the value of .linkdown_irq_regfield for the J784S4 SoC as the "LINK_DOWN" macro corresponding to BIT(1), and as a result, the Link Down interrupts on J784S4 SoC are missed. According to the Technical Reference Manual and Register Documentation for the J784S4 SoC[1], BIT(1) corresponds to "ENABLE_SYS_EN_PCIE_DPA_1", which is not the correct field for the link-state interrupt. Instead, it is BIT(10) of the "PCIE_INTD_ENABLE_REG_SYS_2" register that corresponds to the link-state field named as "ENABLE_SYS_EN_PCIE_LINK_STATE". Thus, set .linkdown_irq_regfield to the macro "J7200_LINK_DOWN", which expands to BIT(10) and was first defined for the J7200 SoC. Other SoCs already reuse this macro since it accurately represents the "link-state" field in their respective "PCIE_INTD_ENABLE_REG_SYS_2" register. 1: https://www.ti.com/lit/zip/spruj52 Fixes: e49ad667815d ("PCI: j721e: Add TI J784S4 PCIe configuration") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> [kwilczynski: commit log, add a missing .linkdown_irq_regfield member set to the J7200_LINK_DOWN macro to struct j7200_pcie_ep_data] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Link: https://lore.kernel.org/r/20250305132018.2260771-1-s-vadapalli@ti.com
2025-03-08PCI: Fix typosBjorn Helgaas1-4/+4
Fix typos and whitespace errors. Link: https://lore.kernel.org/r/20250307231715.438518-1-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2025-03-04PCI: cadence-ep: Fix the driver to send MSG TLP for INTx without data payloadHans Zhang2-3/+2
Per the Cadence's "PCIe Controller IP for AX14" user guide, Version 1.04, Section 9.1.7.1, "AXI Subordinate to PCIe Address Translation Registers", Table 9.4, the bit 16 of the AXI Subordinate Address (axi_s_awaddr) when set corresponds to MSG with data, and when not set, to MSG without data. However, the driver is currently doing the opposite and due to this, the INTx is never received on the host. So, fix the driver to reflect the documentation and also make INTx work. Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller") Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20250214165724.184599-1-18255117159@163.com [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-11-25Merge branch 'pci/controller/j721e'Bjorn Helgaas1-14/+23
- Add PCIe support for J722S SoC (Siddharth Vadapalli) - Delay PCIE_T_PVPERL_MS (100 ms), not just PCIE_T_PERST_CLK_US (100 us), before deasserting PERST# to ensure power and refclk are stable (Siddharth Vadapalli) * pci/controller/j721e: PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds PCI: j721e: Add PCIe support for J722S SoC
2024-11-25Merge branch 'pci/controller/cadence'Bjorn Helgaas1-2/+2
- Lower severity of 'phy-names' message (Bartosz Wawrzyniak) * pci/controller/cadence: PCI: cadence: Lower severity of message when phy-names property is absent in DTS
2024-11-13PCI: cadence: Lower severity of message when phy-names property is absent in DTSBartosz Wawrzyniak1-2/+2
The "phy-names" property is optional, so the message indicating its absence during the probe should be of "info" severity rather than "error" severity. Link: https://lore.kernel.org/r/20241018113045.2050295-1-bwawrzyn@cisco.com Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> [kwilczynski: update log messages wording, commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-11-04PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS millisecondsSiddharth Vadapalli1-14/+12
According to Section 2.2 of the PCI Express Card Electromechanical Specification (Revision 5.1), in order to ensure that the power and the reference clock are stable, PERST# has to be deasserted after a delay of 100 milliseconds (TPVPERL). Currently, it is being assumed that the power is already stable, which is not necessarily true. Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and reference clock are stable. Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver") Fixes: f96b69713733 ("PCI: j721e: Use T_PERST_CLK_US macro") Link: https://lore.kernel.org/r/20241104074420.1862932-1-s-vadapalli@ti.com Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-11-03PCI: j721e: Add PCIe support for J722S SoCSiddharth Vadapalli1-0/+11
TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3 single lane PCIe controller. Add support for the "ti,j722s-pcie-host" compatible specific to J722S SoC. Link: https://lore.kernel.org/r/20240524092349.158443-1-s-vadapalli@ti.com Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-10-03PCI: controller: Switch back to struct platform_driver::remove()Sergio Paracuellos1-1/+1
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all PCI controller drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Link: https://lore.kernel.org/r/20240923065706.728769-1-sergio.paracuellos@gmail.com Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> [bhelgaas: add pcie-xilinx-nwl.c and tidy whitespace per Uwe Kleine-König: https://lore.kernel.org/r/tdxrmmqyzcufupnwkdbg7lwgadizm7v3lxjirykijbml7x54ze@upbdzycdsilm] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-09-19Merge branch 'pci/misc'Bjorn Helgaas1-1/+1
- Check pcie_find_root_port() return in x86 fixups to avoid NULL pointer dereferences (Samasth Norway Ananda) - Make pci_bus_type constant (Kunwu Chan) - Remove unused declarations of __pci_pme_wakeup() and pci_vpd_release() (Yue Haibing) - Remove any leftover .*.cmd files with make clean (zhang jiao) * pci/misc: PCI: Fix typos PCI/VPD: Remove pci_vpd_release() unused declarations PCI/PM: Remove __pci_pme_wakeup() unused declarations PCI: Make pci_bus_type constant x86/PCI: Check pcie_find_root_port() return for NULL
2024-09-19Merge branch 'pci/controller/j721e'Bjorn Helgaas3-35/+181
- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli) - Extract the cadence link setup from cdns_pcie_host_setup() so link setup can be done separately during resume (Thomas Richard) - Use dev_err_probe() to simplify j721e probe (Thomas Richard) - Add T_PERST_CLK_US definition for the mandatory delay between Refclk becoming stable and PERST# being deasserted (Thomas Richard) - Add j721e suspend and resume support (Théo Lebrun) * pci/controller/j721e: PCI: j721e: Add suspend and resume support PCI: j721e: Use T_PERST_CLK_US macro PCI: Add T_PERST_CLK_US macro PCI: j721e: Add reset GPIO to struct j721e_pcie PCI: j721e: Use dev_err_probe() in the probe() function PCI: cadence: Set cdns_pcie_host_init() global PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup() PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property
2024-09-19PCI: Fix typosBjorn Helgaas1-1/+1
Fix typos. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-09-04PCI: j721e: Add suspend and resume supportThéo Lebrun1-6/+92
Add suspend and resume support. Only the Root Complex mode is supported. During the suspend stage PERST# is asserted, then deasserted during the resume stage. Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-7-a2f9156da6c3@bootlin.com Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> [kwilczynski: commit log, update references to the PCI SIG specification] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2024-09-04PCI: j721e: Use T_PERST_CLK_US macroThomas Richard1-1/+1
Use the T_PERST_CLK_US macro, and the fsleep() function instead of usleep_range(). Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-6-a2f9156da6c3@bootlin.com Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-09-03PCI: cadence: Drop excess cdns_pcie_rc.dev kerneldoc descriptionBjorn Helgaas1-1/+0
Struct cdns_pcie_rc once had a .dev member, but it was removed by bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library"). Drop the extra kerneldoc for it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-09-03PCI: j721e: Add reset GPIO to struct j721e_pcieThéo Lebrun1-0/+2
Add reset GPIO to struct j721e_pcie, so it can be used at suspend and resume stages. Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-4-a2f9156da6c3@bootlin.com Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-09-03PCI: j721e: Use dev_err_probe() in the probe() functionThomas Richard1-11/+8
Use dev_err_probe() instead of dev_err() in the probe() function to simplify the code and standardize the error output. Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-3-a2f9156da6c3@bootlin.com Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-09-03PCI: cadence: Set cdns_pcie_host_init() globalThomas Richard2-3/+8
During the resume sequence of the host, cdns_pcie_host_init() needs to be called, so set it global. The dev function parameter is removed, as it isn't used. Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-2-a2f9156da6c3@bootlin.com Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2024-09-03PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()Thomas Richard2-13/+32
The function cdns_pcie_host_setup() mixes probe structure and link setup. The link setup must be done during the resume sequence. So extract it from cdns_pcie_host_setup() and create a dedicated function. Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-1-a2f9156da6c3@bootlin.com Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2024-08-31PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" existsSiddharth Vadapalli1-1/+38
The ACSPCIE module is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on-board and external reference clock generators. Enabling the output from the ACSPCIE module's PAD IO Buffers requires clearing the "PAD IO disable" bits of the ACSPCIE_PROXY_CTRL register in the CTRL_MMR register space. Add support to enable the ACSPCIE reference clock output using the optional device-tree property "ti,syscon-acspcie-proxy-ctrl". Link: https://lore.kernel.org/linux-pci/20240829105316.1483684-3-s-vadapalli@ti.com Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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