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2025-10-01Merge tag 'pinctrl-v6.18-1' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "We have GPIO awareness in the pin control core and an interesting AAEON driver. Core changes: - Allow pins to be identified/marked as GPIO mode with a special callback. The pin controller core is now "aware" if a pin is in GPIO mode if the callback is implemented in the driver, and can thus be marked as "strict", i.e. disallowing simultaneous use of a line as GPIO and another function such as I2C. This is enabled in the Qualcomm TLMM driver and also implemeted from day 1 in the new Broadcom STB driver - Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL to better describe what the config is doing, as well as making it more intuitive what shall be returned when reading this property New drivers: - Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver - Qualcomm Glymur family pin controller driver - Broadcom STB family pin controller driver - Tegra186 pin controller driver - AAEON UP pin controller support. This is some special pin controller that works as an external advanced line MUX and amplifier for signals from an Intel SoC. A cooperative effort with the GPIO maintainer was needed to reach a solution where we reuse code from the GPIO aggregator/forwarder driver - Renesas RZ/T2H and RZ/N2H pin controller support - Axis ARTPEC-8 subdriver for the Samsung pin controller driver Improvements: - Output enable (OEN) support in the Renesas RZG2L driver - Properly support bias pull up/down in the pinctrl-single driver - Move over all GPIO portions using generic MMIO GPIO to the new generic GPIO chip management which has a nice and separate API - Proper DT bindings for some older Broadcom SoCs - External GPIO (EGPIO) support in the Qualcomm SM8250 Deleted code: - Dropped the now unused Samsung S3C24xx drivers" * tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits) pinctrl: use more common syntax for compound literals pinctrl: Simplify printks with pOF format pinctrl: qcom: Add SDM660 LPASS LPI TLMM dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets pinctrl: qcom: Add glymur pinctrl driver dt-bindings: pinctrl: qcom: Add Glymur pinctrl pinctrl: qcom: sm8250: Add egpio support pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL pinctrl: keembay: fix double free in keembay_build_functions() pinctrl: spacemit: fix typo in PRI_TDI pin name pinctrl: eswin: Fix regulator error check and Kconfig dependency pinctrl: bcm: Add STB family pin controller driver dt-bindings: pinctrl: Add support for Broadcom STB pin controller pinctrl: qcom: make the pinmuxing strict pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functions pinctrl: qcom: add infrastructure for marking pin functions as GPIOs pinctrl: allow to mark pin functions as requestable GPIOs pinctrl: qcom: use generic pin function helpers pinctrl: make struct pinfunction a pointer in struct function_desc ...
2025-09-16pinctrl: Add MAX7360 pinctrl driverMathieu Dubois-Briand1-0/+1
Add driver for Maxim Integrated MAX7360 pinctrl on the PORT pins. Pins can be used either for GPIO, PWM or rotary encoder functionalities. Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20250824-mdb-max7360-support-v14-3-435cfda2b1ea@bootlin.com Signed-off-by: Lee Jones <lee@kernel.org>
2025-08-18pinctrl: Add pin controller driver for AAEON UP boardsThomas Richard1-0/+1
This enables the pin control support of the onboard FPGA on AAEON UP boards. This FPGA acts as a level shifter between the Intel SoC pins and the pin header, and also as a mux or switch. +---------+ +--------------+ +---+ | | | | | | PWM0 | \ | | H | |----------|------ \-----|-------------| E | | I2C0_SDA | | | A | Intel SoC |----------|------\ | | D | | GPIO0 | \------|-------------| E | |----------|------ | | R | | | FPGA | | | ----------+ +--------------+ +---+ For most of the pins, the FPGA opens/closes a switch to enable/disable the access to the SoC pin from a pin header. Each switch, has a direction flag that is set depending the status of the SoC pin. For some other pins, the FPGA acts as a mux, and routes one pin (or the other one) to the header. The driver also provides a GPIO chip. It requests SoC pins in GPIO mode, and drives them in tandem with FPGA pins (switch/mux direction). This commit adds support only for UP Squared board. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/20250811-aaeon-up-board-pinctrl-support-v9-10-29f0cbbdfb30@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-02Merge tag 'pinctrl-v6.17-1' of ↵Linus Torvalds1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Nothing stands out, apart from maybe the interesting Eswin EIC7700, a RISC-V SoC I've never seen before. Core changes: - Open code PINCTRL_FUNCTION_DESC() instead of defining a complex macro only used in one place - Add pinmux_generic_add_pinfunction() helper and use this in a few drivers New drivers: - Amlogic S7, S7D and S6 pin control support - Eswin EIC7700 pin control support - Qualcomm PMIV0104, PM7550 and Milos pin control support Because of unhelpful numbering schemes, the Qualcomm driver now needs to start to rely on SoC codenames - STM32 HDP pin control support - Mediatek MT8189 pin control support Improvements: - Switch remaining pin control drivers over to the new GPIO set callback that provides a return value - Support RSVD (reserved) pins in the STM32 driver - Move many fixed assignments over to pinctrl_desc definitions - Handle multiple TLMM regions in the Qualcomm driver" * tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits) pinctrl: mediatek: Add pinctrl driver for mt8189 dt-bindings: pinctrl: mediatek: Add support for mt8189 pinctrl: aspeed-g6: Add PCIe RC PERST pin group pinctrl: ingenic: use pinmux_generic_add_pinfunction() pinctrl: keembay: use pinmux_generic_add_pinfunction() pinctrl: mediatek: moore: use pinmux_generic_add_pinfunction() pinctrl: airoha: use pinmux_generic_add_pinfunction() pinctrl: equilibrium: use pinmux_generic_add_pinfunction() pinctrl: provide pinmux_generic_add_pinfunction() pinctrl: pinmux: open-code PINCTRL_FUNCTION_DESC() pinctrl: ma35: use new GPIO line value setter callbacks MAINTAINERS: add Clément Le Goffic as STM32 HDP maintainer pinctrl: stm32: Introduce HDP driver dt-bindings: pinctrl: stm32: Introduce HDP pinctrl: qcom: Add Milos pinctrl driver dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer pinctrl: qcom: spmi: Add PM7550 dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support pinctrl: qcom: spmi: Add PMIV0104 dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support ...
2025-06-18pinctrl: eswin: Add EIC7700 pinctrl driverYulin Lu1-0/+1
Add support for the pin controller in ESWIN's EIC7700 SoC, which supports pin multiplexing, pin configuration, and rgmii voltage control. Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Yulin Lu <luyulin@eswincomputing.com> Link: https://lore.kernel.org/20250612105159.1241-1-luyulin@eswincomputing.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-06-18pinctrl: starfive: Allow compile testing on other platformsKrzysztof Kozlowski1-1/+1
Always descent to drivers/pinctrl/starfive/ because limiting it with SOC_STARFIVE is redundant since its Makefile doesn't build anything if no Starfive-specific pin control Kconfig options are enabled. This allows compile testing on other architectures with allyesconfig. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/20250611-pinctrl-const-desc-v2-1-b11c1d650384@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-06-16pinctrl: rp1: Implement RaspberryPi RP1 gpio supportAndrea della Porta1-0/+1
The RP1 is an MFD supporting a gpio controller and /pinmux/pinctrl. Add minimum support for the gpio only portion. The driver is in pinctrl folder since upcoming patches will add the pinmux/pinctrl support where the gpio part can be seen as an addition. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250529135052.28398-5-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-03-05pinctrl: amd: isp411: Add amdisp GPIO pinctrlPratap Nirujogi1-0/+1
Add pinctrl driver support for AMD SoC with isp41 hw ip block. Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Link: https://lore.kernel.org/20250304232051.2936557-1-pratap.nirujogi@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-10-19pinctrl: spacemit: add support for SpacemiT K1 SoCYixun Lan1-0/+1
SpacemiT's K1 SoC has a pinctrl controller which use single register to describe all functions, which include bias pull up/down(strong pull), drive strength, schmitter trigger, slew rate, mux mode. Signed-off-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/20241016-02-k1-pinctrl-v5-2-03d395222e4f@gentoo.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-10-01pinctrl: canaan: Add support for k230 SoCZe Huang1-0/+1
Configuration of the K230 is similar to that of the K210. However, in K210, the 256 functions for each pin are shared, whereas in K230, multiplex functions are different for every pin. `drv_data` of `pinctrl_pin_desc` is pointing to currently activated group, which is used to print the name of current function of pin in `pin_dbg_show` and will be updated in `set_mux`, so they are not set const. Signed-off-by: Ze Huang <18771902331@163.com> Link: https://lore.kernel.org/20240926-k230-pinctrl-v2-2-a9a36fba4b34@163.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-10-01pinctrl: Add driver for the T-Head TH1520 SoCEmil Renner Berthing1-0/+1
Add pinctrl driver for the T-Head TH1520 RISC-V SoC. Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [dfustini: use thead,pad-group to identify the pin controller instance] Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> Link: https://lore.kernel.org/20240930-th1520-pinctrl-v3-2-32cea2bdbecb@tenstorrent.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-09-26Merge tag 'soc-ep93xx-dt-6.12' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC update from Arnd Bergmann: "Convert ep93xx to devicetree This concludes a long journey towards replacing the old board files with devictree description on the Cirrus Logic EP93xx platform. Nikita Shubin has been working on this for a long time, for details see the last post on https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/" * tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config net: cirrus: use u8 for addr to calm down sparse dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0 dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe() pinctrl: ep93xx: Fix raster pins typo spi: ep93xx: update kerneldoc comments for ep93xx_spi clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate() clk: ep93xx: add module license dmaengine: cirrus: remove platform code ASoC: cirrus: edb93xx: Delete driver ARM: ep93xx: soc: drop defines ARM: ep93xx: delete all boardfiles ata: pata_ep93xx: remove legacy pinctrl use pwm: ep93xx: drop legacy pinctrl ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms ARM: dts: ep93xx: Add EDB9302 DT ARM: dts: ep93xx: add ts7250 board ARM: dts: add Cirrus EP93XX SoC .dtsi ...
2024-09-12pinctrl: add a Cirrus ep93xx SoC pin controllerNikita Shubin1-0/+1
Add a pin control (only multiplexing) driver for ep93xx SoC so we can fully convert ep93xx to device tree. This driver is capable of muxing ep9301/ep9302/ep9307/ep9312/ep9315 variants, this is chosen based on "compatible" in device tree. Co-developed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-08-26Merge branch 'ib-sophgo-pintrl' into develLinus Walleij1-0/+1
Immutable branch for the SoC tree, merge to pinctrl devel proper. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-26pinctrl: sophgo: add support for CV1800B SoCInochi Amaoto1-0/+1
Sophgo CV1800 series SoCs share common control logic but have different register mapping. For maintenance, split the driver and pin definition of the SoC. Add base driver for CV1800 series SoC and pin definition of CV1800B. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://lore.kernel.org/IA1PR20MB4953B260E04EC53F6A01EB30BBB32@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-04pinctrl: eyeq5: add platform driverThéo Lebrun1-0/+1
Add the Mobileye EyeQ5 pin controller driver. It belongs to a syscon region called OLB and gets spawned as auxiliary device to the platform driver for clock. Existing pins and their function live statically in the driver code rather than in the devicetree, see compatible match data. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/20240730-mbly-pinctrl-v2-2-d470f64e0395@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-04-19pinctrl: Implementation of the generic scmi-pinctrl driverPeng Fan1-0/+1
scmi-pinctrl driver implements pinctrl driver interface and using SCMI protocol to redirect messages from pinctrl subsystem SDK to SCMI platform firmware, which does the changes in HW. Co-developed-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240418-pinctrl-scmi-v11-4-499dca9864a7@nxp.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2024-03-05pinctrl: Add driver for Awinic AW9523/B I2C GPIO ExpanderAngeloGioacchino Del Regno1-0/+1
The Awinic AW9523(B) is a multi-function I2C gpio expander in a TQFN-24L package, featuring PWM (max 37mA per pin, or total max power 3.2Watts) for LED driving capability. It has two ports with 8 pins per port (for a total of 16 pins), configurable as either PWM with 1/256 stepping or GPIO input/output, 1.8V logic input; each GPIO can be configured as input or output independently from each other. This IC also has an internal interrupt controller, which is capable of generating an interrupt for each GPIO, depending on the configuration, and will raise an interrupt on the INTN pin to advertise this to an external interrupt controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: David Bauer <mail@david-bauer.net> Link: https://lore.kernel.org/r/20210624214458.68716-2-mail@david-bauer.net Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240301-awinic-aw9523-v8-1-7ec572f5dfb4@linaro.org
2023-12-12Merge tag 'pef2256-framer' into develLinus Walleij1-0/+1
Immutable tag for the PEF2256 framer
2023-12-12pinctrl: Add support for the Lantic PEF2256 pinmuxHerve Codina1-0/+1
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. This kind of component can be found in old telecommunication system. It was used to digital transmission of many simultaneous telephone calls by time-division multiplexing. Also using HDLC protocol, WAN networks can be reached through the framer. This pinmux support handles the pin muxing part (pins RP(A..D) and pins XP(A..D)) of the PEF2256. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231128132534.258459-5-herve.codina@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-14pinctrl: tps6594: Add driver for TPS6594 pinctrl and GPIOsEsteban Blanc1-0/+1
TI TPS6594 PMIC has 11 GPIOs which can be used for different functions. This patch adds a pinctrl and GPIO drivers in order to use those functions. Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231108104124.2818275-1-eblanc@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-20pinctrl: realtek: Add common pinctrl driver for Realtek DHC RTD SoCsTzuyi Chang1-0/+1
The RTD SoCs share a similar design for pinmux and pinconfig. This common pinctrl driver supports different variants within the RTD SoCs. Signed-off-by: Tzuyi Chang <tychang@realtek.com> Link: https://lore.kernel.org/r/20230919101117.4097-2-tychang@realtek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-15pinctrl: pinctrl-oxnas: remove obsolete pinctrl driverNeil Armstrong1-1/+0
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 pinctrl & gpio. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Daniel Golle <daniel@makrotopia.org> Acked-by: Andy Shevchenko <andy@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-04a0c5cdda52@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: allow true compile testingKrzysztof Kozlowski1-1/+1
Makefile selected Qualcomm pinctrl drivers only for ARCH_QCOM, making any COMPILE_TEST options inside Kconfig ((ARCH_QCOM || COMPILE_TEST) or (OF || COMPILE_TEST)) not effective. Always descent to the qcom subdirectory to fix this. All individual drivers are selected in Makefile via dedicated CONFIG entries, thus this should not have functional impact except when compile testing. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601152026.1182648-6-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-04-04pinctrl: Remove Intel Thunder Bay pinctrl driverLakshmi Sowjanya D1-1/+0
Remove Thunder Bay specific code as the product got cancelled and there are no end customers or users. Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Link: https://lore.kernel.org/r/20230403120235.939-1-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19pinctrl: mlxbf3: Add pinctrl driver supportAsmaa Mnebhi1-0/+1
NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs or take the default hardware functionality. Add a driver for the pin muxing. Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230315215027.30685-3-asmaa@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19pinctrl: ralink: move to mediatek as mtmipsArınç ÜNAL1-1/+0
This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek introduced new SoCs which utilise this platform. Move the driver to mediatek pinctrl directory. Rename the ralink core driver to mtmips. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Link: https://lore.kernel.org/r/20230317213011.13656-5-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-06pinctrl: add NXP S32 SoC family supportChester Lin1-0/+1
Add the pinctrl driver for NXP S32 SoC family. This driver is mainly based on NXP's downstream implementation on nxp-auto-linux repo[1]. [1] https://github.com/nxp-auto-linux/linux/tree/bsp35.0-5.15.73-rt/drivers/pinctrl/freescale Signed-off-by: Matthew Nunez <matthew.nunez@nxp.com> Signed-off-by: Phu Luu An <phu.luuan@nxp.com> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@nxp.com> Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com> Signed-off-by: Chester Lin <clin@suse.com> Link: https://lore.kernel.org/r/20230220023320.3499-3-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-17pinctrl: pinctrl-loongson2: add pinctrl driver supportzhanghongchen1-0/+1
The Loongson-2 SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing. There is currently no support for GPIO pin pull-up and pull-down. Signed-off-by: zhanghongchen <zhanghongchen@loongson.cn> Co-developed-by: Yinbo Zhu <zhuyinbo@loongson.cn> Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Link: https://lore.kernel.org/r/20221114024942.8111-1-zhuyinbo@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-10-04pinctrl: Create subdirectory for StarFive driversJianlong Huang1-1/+1
Move the StarFive JH7100 pinctrl driver to a new subdirectory in preparation for adding more StarFive pinctrl drivers. No functional change. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> Link: https://lore.kernel.org/r/20220930060819.5320-1-hal.feng@linux.starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-08-25pinctrl: Add Cypress cy8c95x0 supportPatrick Rudolph1-0/+1
Add support for cypress I2C GPIO expanders cy8c9520, cy8c9540 and cy8c9560. The GPIO expanders feature a PWM mode, thus add it as pinctrl driver. The chip features multiple drive modes for each pin when configured as output and multiple bias settings when configured as input. Tested all three components and verified that all functionality is fully working. Datasheet: https://www.cypress.com/file/37971/download Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Link: https://lore.kernel.org/r/20220816054917.7893-3-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-03-15pinctrl: nuvoton: Add driver for WPCM450Jonathan Neuschäfer1-1/+1
This driver is based on the one for NPCM7xx, because the WPCM450 is a predecessor of those SoCs. Notable differences: - On WPCM450, the GPIO registers are not organized in multiple banks, but rather placed continually into the same register block. This affects how register offsets are computed. - Pinmux nodes can explicitly select GPIO mode, whereas in the npcm7xx driver, this happens automatically when a GPIO is requested. Some functionality implemented in the hardware was (for now) left unused in the driver, specifically blinking and pull-up/down. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20220129115228.2257310-6-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-28Merge tag 'intel-pinctrl-v5.18-1' of ↵Linus Walleij1-1/+1
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.18-1 * Introduce support for Alder Lake-N (required to revert misplaced ID) * Add support for Raptor Lake-S * Add support for Ice Lake-N (MacBookPro16,2) * Miscellaneous fixes The following is an automated git shortlog grouped by driver: alderlake: - Add Intel Alder Lake-N pin controller support - Add Raptor Lake-S ACPI ID baytrail: - Clear direct_irq_en flag on broken configs icelake: - Add Ice Lake-N PCH pin controller support intel: - Fix a glitch when updating IRQ flags on a preconfigured line - fix unexpected interrupt Place correctly CONFIG_PINCTRL_ST in the Makefile: - Place correctly CONFIG_PINCTRL_ST in the Makefile tigerlake: - Revert "Add Alder Lake-M ACPI ID"
2022-01-30pinctrl: Add driver for Sunplus SP7021Wells Lu1-0/+1
Add driver for Sunplus SP7021 SoC. Signed-off-by: Wells Lu <wellslutw@gmail.com> Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-24pinctrl: Place correctly CONFIG_PINCTRL_ST in the MakefileAndy Shevchenko1-1/+1
Keep Makefile entries ordered in the same way as Kconfig ones. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-01-12Merge tag 'pinctrl-v5.17-1' of ↵Linus Torvalds1-23/+25
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control bulk updates from Linus Walleij: "Core changes: - New standard enumerator and corresponding device tree bindings for output impedance pin configuration. (Implemented and used in the Renesas rzg2l driver.) - Cleanup of Kconfig and Makefile to be somewhat orderly and alphabetic. New drivers: - Samsung Exynos 7885 pin controller. - Ocelot LAN966x pin controller. - Qualcomm SDX65 pin controller. - Qualcomm SM8450 pin controller. - Qualcomm PM8019, PM8226 and PM2250 pin controllers. - NXP/Freescale i.MXRT1050 pin controller. - Intel Thunder Bay pin controller. Enhancements: - Introduction of the string library helper function "kasprintf_strarray()" and subsequent use in Rockchip, ST and Armada pin control drivers, as well as the GPIO mockup driver. - The Ocelot pin controller has been extensively rewritten to use regmap and other modern kernel infrastructure. - The Microchip SGPIO driver has been converted to use regmap. - The SPEAr driver had been converted to use regmap. - Substantial cleanups and janitorial on the Apple pin control driver that was merged for v5.16. - Janitorial to remove of_node assignments in the GPIO portions that anyway get this handled in the GPIO core. - Minor cleanups and improvements in several pin controllers" * tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (98 commits) pinctrl: imx: fix assigning groups names dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations pinctrl: bcm: ns: use generic groups & functions helpers pinctrl: imx: fix allocation result check pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt pinctrl: Propagate firmware node from a parent device dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings pinctrl: add one more "const" for generic function groups pinctrl: keembay: rework loops looking for groups names pinctrl: keembay: comment process of building functions a bit pinctrl: imx: prepare for making "group_names" in "function_desc" const ARM: dts: gpio-ranges property is now required pinctrl: aspeed: fix unmet dependencies on MFD_SYSCON for PINCTRL_ASPEED pinctrl: Get rid of duplicate of_node assignment in the drivers pinctrl-sunxi: don't call pinctrl_gpio_direction() pinctrl-bcm2835: don't call pinctrl_gpio_direction() pinctrl: bcm2835: Silence uninit warning pinctrl: Sort Kconfig and Makefile entries alphabetically pinctrl: Add Intel Thunder Bay pinctrl driver dt-bindings: pinctrl: Add bindings for Intel Thunderbay pinctrl driver ...
2021-12-16pinctrl: starfive: Add pinctrl driver for StarFive SoCsEmil Renner Berthing1-0/+1
Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which is said to feature only minor changes to these pinctrl/GPIO parts. For each "GPIO" there are two registers for configuring the output and output enable signals which may come from other peripherals. Among these are two special signals that are constant 0 and constant 1 respectively. Controlling the GPIOs from software is done by choosing one of these signals. In other words the same registers are used for both pin muxing and controlling the GPIOs, which makes it easier to combine the pinctrl and GPIO driver in one. I wrote the pinconf and pinmux parts, but the GPIO part of the code is based on the GPIO driver in the vendor tree written by Huan Feng with cleanups and fixes by Drew and me. Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Co-developed-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Co-developed-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-09pinctrl: Sort Kconfig and Makefile entries alphabeticallyAndy Shevchenko1-23/+24
Sort Kconfig and Makefile entries alphabetically for better maintenance in the future. While at it fix some style issues, such as: - "Say Y"/"Say yes"/"Say Yes" --> "Say Y" - "pullup/pulldown" --> "pull-up and pull-down" - wrong indentation Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211209113456.33977-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-09pinctrl: Add Intel Thunder Bay pinctrl driverLakshmi Sowjanya D1-0/+1
About Intel Thunder Bay: ----------------------- Intel Thunder Bay is a computer vision AI accelerator SoC based on ARM CPU. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Thunder Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Thunder Bay SoC. Co-developed-by: Kiran Kumar S <kiran.kumar1.s@intel.com> Signed-off-by: Kiran Kumar S <kiran.kumar1.s@intel.com> Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Link: https://lore.kernel.org/r/20211201072626.19599-3-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-27pinctrl: add pinctrl/GPIO driver for Apple SoCsJoey Gouly1-0/+1
This driver adds support for the pinctrl / GPIO hardware found on some Apple SoCs. Co-developed-by: Stan Skowronek <stan@corellium.com> Signed-off-by: Stan Skowronek <stan@corellium.com> Signed-off-by: Joey Gouly <joey.gouly@arm.com> Acked-by: Hector Martin <marcan@marcan.st> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211026175815.52703-5-joey.gouly@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: Add Intel Keem Bay pinctrl driverLakshmi Sowjanya D1-0/+1
About Intel Keem Bay: ------------------- Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU. Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Keem Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC. Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Reviewed-by: Mark Gross <mgross@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-22pinctrl: Add Xilinx ZynqMP pinctrl driver supportSai Krishna Potthuri1-0/+1
Adding pinctrl driver for Xilinx ZynqMP platform. This driver queries pin information from firmware and registers pin control accordingly. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1619080202-31924-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-26Merge tag 'riscv-for-linus-5.12-mw0' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: "A handful of new RISC-V related patches for this merge window: - A check to ensure drivers are properly using uaccess. This isn't manifesting with any of the drivers I'm currently using, but may catch errors in new drivers. - Some preliminary support for the FU740, along with the HiFive Unleashed it will appear on. - NUMA support for RISC-V, which involves making the arm64 code generic. - Support for kasan on the vmalloc region. - A handful of new drivers for the Kendryte K210, along with the DT plumbing required to boot on a handful of K210-based boards. - Support for allocating ASIDs. - Preliminary support for kernels larger than 128MiB. - Various other improvements to our KASAN support, including the utilization of huge pages when allocating the KASAN regions. We may have already found a bug with the KASAN_VMALLOC code, but it's passing my tests. There's a fix in the works, but that will probably miss the merge window. * tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits) riscv: Improve kasan population by using hugepages when possible riscv: Improve kasan population function riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization riscv: Improve kasan definitions riscv: Get rid of MAX_EARLY_MAPPING_SIZE soc: canaan: Sort the Makefile alphabetically riscv: Disable KSAN_SANITIZE for vDSO riscv: Remove unnecessary declaration riscv: Add Canaan Kendryte K210 SD card defconfig riscv: Update Canaan Kendryte K210 defconfig riscv: Add Kendryte KD233 board device tree riscv: Add SiPeed MAIXDUINO board device tree riscv: Add SiPeed MAIX GO board device tree riscv: Add SiPeed MAIX DOCK board device tree riscv: Add SiPeed MAIX BiT board device tree riscv: Update Canaan Kendryte K210 device tree dt-bindings: add resets property to dw-apb-timer dt-bindings: fix sifive gpio properties dt-bindings: update sifive uart compatible string dt-bindings: update sifive clint compatible string ...
2021-02-18pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driverDamien Le Moal1-0/+1
Add the pinctrl-k210.c pinctrl driver for the Canaan Kendryte K210 field programmable IO array (FPIOA) to allow configuring the SoC pin functions. The K210 has 48 programmable pins which can take any of 256 possible functions. This patch is inspired from the k210 pinctrl driver for the u-boot project and contains many direct contributions from Sean Anderson. The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210 SOC FPIOA DRIVER" with myself listed as maintainer for this driver. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-01-21pinctrl: remove ste u300 driverArnd Bergmann1-1/+0
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-6-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: remove coh901 driverArnd Bergmann1-1/+0
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-5-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: remove sirf atlas/prima driversArnd Bergmann1-1/+0
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: remove zte zx driverArnd Bergmann1-1/+0
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-3-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-12-16Merge tag 'pinctrl-v5.11-1' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.11 kernel. Drivers, drivers and drivers. Not a single core change. Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot SoCs. As part of the modularization attempt, I applied one patch affecting the firmware subsystem as a functional (not syntactic/semantic) dependency and then it blew up in our face, so I had to revert it, bummer. It will come in later, through that subsystem, I guess. New drivers: - New driver for the Microchip Serial GPIO "SGPIO". - Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver. New subdrivers: - Intel Lakefield subdriver. - Intel Elkhart Lake subdriver. - Intel Alder Lake-S subdriver. - Qualcomm MSM8953 subdriver. - Qualcomm SDX55 subdriver. - Qualcomm SDX55 PMIC subdriver. - Ocelot Luton SoC subdriver. - Ocelot Serval SoC subdriver. Modularization: - The Meson driver can now be built as modules. - The Qualcomm driver(s) can now be built as modules. Incremental improvements: - The Intel driver now supports pin configuration for GPIO-related configurations. - A bunch of Renesas PFC drivers have been augmented with support for QSPI pins, groups and functions. - Non-critical fixes to the irq handling in the Allwinner Sunxi driver" * tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl/spear: simplify the return expression of spear300_pinctrl_probe() pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1() dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5) pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom-pmic-gpio: Add support for pmx55 dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error pinctrl: mtk: Fix low level output voltage issue pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe() pinctrl: actions: pinctrl-s500: Constify s500_padinfo[] pinctrl: pinctrl-microchip-sgpio: Add OF config dependency pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver pinctrl: at91-pio4: add support for fewer lines on last PIO bank pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller ...
2020-12-08pinctrl: ralink: add a pinctrl driver for the rt2880 familySergio Paracuellos1-0/+1
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each pin individually, these socs have mux groups that when set will effect 1-N pins. Pin groups have a 2, 4 or 8 different muxes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-27 23:54:09 +0000