linux - Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/

Age	Commit message (Expand)	Author	Files	Lines
2025-09-21	memstick: drop nth_page() usage within SG entry	David Hildenbrand	2	-4/+2
2025-09-21	mspro_block: drop nth_page() usage within SG entry	David Hildenbrand	1	-2/+1
2025-09-21	drm/i915/gem: drop nth_page() usage within SG entry	David Hildenbrand	1	-1/+1
2025-09-21	ata: libata-sff: drop nth_page() usage within SG entry	David Hildenbrand	1	-3/+3
2025-09-21	Merge branch 'mm-hotfixes-stable' into mm-stable in order to pick up	Andrew Morton	1	-5/+3
2025-09-21	reset: aspeed: register AST2700 reset auxiliary bus device	Ryan Chen	3	-0/+261
2025-09-21	clk: tegra: do not overallocate memory for bpmp clocks	Fedor Pchelkin	1	-1/+1
2025-09-21	clk: ep93xx: Use int type to store negative error codes	Qianfeng Rong	1	-1/+2
2025-09-21	clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver	Alok Tiwari	1	-2/+2
2025-09-21	clk: loongson2: Add clock definitions for Loongson-2K0300 SoC	Yao Zi	1	-0/+46
2025-09-21	clk: loongson2: Avoid hardcoding firmware name of the reference clock	Yao Zi	1	-16/+17
2025-09-21	clk: loongson2: Allow zero divisors for dividers	Yao Zi	1	-1/+2
2025-09-21	clk: loongson2: Support scale clocks with an alternative mode	Yao Zi	1	-3/+23
2025-09-21	clk: loongson2: Allow specifying clock flags for gate clock	Yao Zi	1	-1/+15
2025-09-21	Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds	2	-2/+20
2025-09-21	clk: clocking-wizard: Fix output clock register offset for Versal platforms	Shubhrajyoti Datta	1	-1/+1
2025-09-21	clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()	Shubhrajyoti Datta	1	-14/+18
2025-09-21	clk: mmp: pxa1908: Instantiate power driver through auxiliary bus	Duje Mihanović	4	-1/+22
2025-09-21	clk: s2mps11: add support for S2MPG10 PMIC clock	André Draszik	1	-0/+8
2025-09-21	clk: stm32: introduce clocks for STM32MP21 platform	Gabriel Fernandez	4	-0/+2245
2025-09-21	clk: Use hashtable for global clk lookups	Chen-Yu Tsai	1	-32/+18
2025-09-21	clk: Sort include statements	Chen-Yu Tsai	1	-8/+8
2025-09-21	clk: st: flexgen: remove unused compatible	Raphael Gallais-Pou	1	-80/+0
2025-09-21	clk: mediatek: Add MT8196 vencsys clock support	Laura Nao	3	-0/+244
2025-09-21	clk: mediatek: Add MT8196 vdecsys clock support	Laura Nao	3	-0/+261
2025-09-21	clk: mediatek: Add MT8196 ovl1 clock support	Laura Nao	2	-1/+155
2025-09-21	clk: mediatek: Add MT8196 ovl0 clock support	Laura Nao	2	-1/+156
2025-09-21	clk: mediatek: Add MT8196 disp-ao clock support	Laura Nao	2	-1/+81
2025-09-21	clk: mediatek: Add MT8196 disp1 clock support	Laura Nao	2	-1/+171
2025-09-21	clk: mediatek: Add MT8196 disp0 clock support	Laura Nao	3	-0/+178
2025-09-21	clk: mediatek: Add MT8196 mfg clock support	Laura Nao	3	-0/+158
2025-09-21	clk: mediatek: Add MT8196 mdpsys clock support	Laura Nao	3	-0/+194
2025-09-21	clk: mediatek: Add MT8196 mcu clock support	Laura Nao	3	-0/+175
2025-09-21	clk: mediatek: Add MT8196 I2C clock support	Laura Nao	3	-0/+126
2025-09-21	clk: mediatek: Add MT8196 pextpsys clock support	Laura Nao	3	-0/+139
2025-09-21	clk: mediatek: Add MT8196 ufssys clock support	Laura Nao	3	-0/+116
2025-09-21	clk: mediatek: Add MT8196 peripheral clock support	Laura Nao	2	-1/+144
2025-09-21	clk: mediatek: Add MT8196 vlpckgen clock support	Laura Nao	2	-1/+726
2025-09-21	clk: mediatek: Add MT8196 topckgen2 clock support	Laura Nao	2	-1/+570
2025-09-21	clk: mediatek: Add MT8196 topckgen clock support	Laura Nao	2	-1/+986
2025-09-21	clk: mediatek: Add MT8196 apmixedsys clock support	Laura Nao	3	-0/+213
2025-09-21	clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro	Laura Nao	1	-0/+19
2025-09-21	clk: mediatek: clk-gate: Add ops for gates with HW voter	Laura Nao	2	-3/+71
2025-09-21	clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct	Laura Nao	1	-33/+19
2025-09-21	clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC	Laura Nao	3	-1/+114
2025-09-21	clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()	Laura Nao	2	-0/+17
2025-09-21	clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC	Laura Nao	2	-0/+94
2025-09-21	clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC	Laura Nao	2	-1/+44
2025-09-21	clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control	Laura Nao	2	-0/+8
2025-09-21	clk: mediatek: clk-mux: Do not pass flags to clk_mux_determine_rate_flags()	Chen-Yu Tsai	1	-3/+1