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2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola-0/+1
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola-0/+58
2025-11-19scsi: snic: Switch to use %ptSpAndy Shevchenko-9/+6
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola-0/+69
2025-11-19scsi: fnic: Switch to use %ptSpAndy Shevchenko-32/+25
2025-11-19s390/dasd: Switch to use %ptSpAndy Shevchenko-2/+1
2025-11-19ptp: ocp: Switch to use %ptSpAndy Shevchenko-8/+5
2025-11-19pps: Switch to use %ptSpAndy Shevchenko-4/+2
2025-11-19PCI: epf-test: Switch to use %ptSpAndy Shevchenko-3/+2
2025-11-19net: dsa: sja1105: Switch to use %ptSpAndy Shevchenko-5/+3
2025-11-19mmc: mmc_test: Switch to use %ptSpAndy Shevchenko-12/+8
2025-11-19media: av7110: Switch to use %ptSpAndy Shevchenko-1/+1
2025-11-19ipmi: Switch to use %ptSpAndy Shevchenko-6/+3
2025-11-19igb: Switch to use %ptSpAndy Shevchenko-5/+2
2025-11-19e1000e: Switch to use %ptSpAndy Shevchenko-5/+2
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko-2/+2
2025-11-19drm/vblank: Switch to use %ptSpAndy Shevchenko-4/+2
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola-35/+40
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola-0/+19
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola-117/+0
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak-3/+15
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak-1/+3
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak-12/+5
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak-7/+36
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak-0/+25
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak-2/+8
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak-7/+49
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak-1/+6
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak-105/+98
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak-32/+92
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak-21/+47
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak-9/+14
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak-27/+35
2025-11-19drm/i915/cx0: Rename TBT functions to be ICL specificMika Kahola-15/+15
2025-11-19gpio: cdev: make sure the cdev fd is still active before emitting eventsBartosz Golaszewski-2/+7
2025-11-19pwm: bcm2835: Make sure the channel is enabled after pwm_request()Uwe Kleine-König-25/+3
2025-11-19drm/msm: Switch to use %ptSpAndy Shevchenko-4/+2
2025-11-19drm/amdgpu: Switch to use %ptSpAndy Shevchenko-2/+1
2025-11-19dma-buf: Switch to use %ptSpAndy Shevchenko-1/+1
2025-11-19drm/i915/fbdev: Hold runtime PM ref during fbdev BO creationDibin Moolakadan Subrahmanian-4/+7
2025-11-19gpio: shared: extend the ifdef guard to gpio_shared_find_entry()Bartosz Golaszewski-1/+1
2025-11-19gpio: shared: fix a NULL-pointer dereferenceBartosz Golaszewski-1/+4
2025-11-18drm/xe/vf: Shadow buffer management for CCS read/write operationsSatyanarayana K V P-7/+73
2025-11-18drm/xe/sa: Shadow buffer support in the sub-allocator poolSatyanarayana K V P-4/+91
2025-11-18net/mlx5: Use EOPNOTSUPP instead of ENOTSUPPTariq Toukan-8/+8
2025-11-18net/mlx5: Abort new commands if all command slots are stalledSaeed Mahameed-0/+55
2025-11-18net/mlx5: Remove redundant bw_share minimal value assignmentCarolina Jubran-7/+0
2025-11-18net/mlx5e: Recover SQ on excessive PTP TX timestamp deltaCarolina Jubran-8/+17
2025-11-18net/mlx5: Refactor EEPROM query error handling to return status separatelyGal Pressman-28/+30
2025-11-18net/mlx5: Clean up only new IRQ glue on request_irq() failurePradyumn Rahar-4/+2
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