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path: root/include/asm-mips/cpu.h
AgeCommit message (Expand)AuthorLines
2008-01-29[MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss-2/+2
2007-10-11[MIPS] Convert list of CPU types from #define to enum.Ralf Baechle-70/+49
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle-18/+17
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno-2/+10
2007-07-10[MIPS] PMC MSP71xx mips commonMarc St-Jean-0/+2
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang-1/+6
2007-07-10[MIPS] Enable support for the userlocal hardware registerRalf Baechle-0/+1
2007-07-06[MIPS] Add macros to encode processor revisions.Ralf Baechle-0/+11
2006-07-13[MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle-1/+1
2006-06-01[MIPS] Treat R14000 like R10000.Kumba-1/+3
2006-06-01[MIPS] Fix detection and handling of the 74K processor.Chris Dearman-1/+3
2006-02-14[MIPS] Fix CPU type bitmasks for MIPS III, IV and V.Maciej W. Rozycki-3/+3
2006-01-10MIPS: Reorganize ISA constants strictly as bitmasks.Ralf Baechle-7/+10
2006-01-10MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle-1/+3
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle-10/+7
2005-10-29Add support for SB1A CPU.Andrew Isaacson-1/+3
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle-19/+21
2005-10-29Move MIPS Technologies processor IDs to where they belong.Maciej W. Rozycki-2/+7
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov-1/+3
2005-10-29Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle-0/+4
2005-10-29Detect the 34K.Ralf Baechle-1/+3
2005-10-29Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle-0/+2
2005-10-29Cleanup decoding of MIPSxx config registers.Ralf Baechle-1/+9
2005-10-29Base Au1200 2.6 support.Pete Popov-1/+2
2005-10-29Add a few more PrId vendor IDs.Ralf Baechle-6/+11
2005-04-16Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds-0/+222
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